The PDP-11 FAQ Introduction The PDP-11 was, and is, an extremely successful and influential family of machines which has spanned over two decades from the early 1970s through the mid 1990s. This note is an attempt to gather some of the knowledge on this family and present it for the benefit of those who are enthusiasts, curious, or downright confused as to what the -11 was and is, and how it related and still relates to its world. The information presented is compiled from the memory and notebooks of both myself and a number of people who have filled in the many gaps in my memory or set me straight on certain details. Feel free to mail any of the maintainers at faq11 @ village.org with any data you feel should be included, corrected or updated. Contents - What is a PDP? - What is a PDP-11? - What different PDP-11 models were made? - What did a PDP-11 Cost? - Differences between the 11/70 and the 11/83, 11/93. - Other fun PDP11's. - The Never 11's - Non-DEC 11's - Warsaw Pact PDP-11 clones - Part Number Format - PDP-11 Relative Performance - What operating systems were written for the PDP-11? - What programming languages are supported on the PDP-11? - Hobbyist licenses for PDP-11 operating systems - Memory address convention (for this FAQ), and the GPRs - What is the PDP-11 instruction set? - Parity Registers on the 11/45 - How Do I Set The Jumpers On... - The PDP-11 Maintenance Panel and front panel - Trivia/Humour/Stories - Who's Who? - Mark Crispin's 1986 list of PDP's - Appendix A: Related FAQ Sites - Appendix B: Where can I buy [whatever] for my PDP-11? - Editors/Maintainers of the PDP-11 FAQ - Revision History Last updated: Sat Jun 10 13:30:25 2000 ======================================================== What is a PDP? Extracted from the PDP-8 FAQ By Doug Jones. Used with his permission. Digital Equipment Corporation (DEC) was founded in 1957, with facilities in an old woolen mill in Maynard Massachusetts; at first, they sold transistorized "systems modules", plug-in circuit boards with a few transistorized logic gates per board. Starting in 1960, though, DEC began to experiment with selling computers; by 1961, they had sold enough that DECUS, the Digital Equipment Computer User's Society was founded. DEC's first computer, the PDP-1, sold for only $120,000 at a time when other computers sold for over $1,000,000. Everyone (the government and DEC's stockholders included) knew that computers were big and expensive and needed a computer center and a large staff; DEC chose to avoid dealing with these stereotypes by entirely avoiding the term "computer"; thus, for over a decade, all digital computers sold by DEC were called Programmed Data Processors (PDPs). In early DEC documentation, plural form "PDPs" is used as a generic term for all DEC computers. [Ken Olsen claimed that the board of directors would not let him call the machines computers because some contemporary study had predicted that the world market for computers would be very small - less than 100 if memory serves. They were mollified with Programmed Data Processor, however, and PDP lives to this day. -MMcC] DEC built a number of different computers under the PDP label, with a huge range of price and performance. The largest of these are fully worthy of large computer centers with big support staffs. Many early DEC computers were not really built by DEC. With the PDP-3 and LINC, for example, customers built the machines using DEC parts and facilities. Here is the list of PDP computers: MODEL DATE PRICE BITS COMMENTS ===== ==== ======== ==== ===== PDP-1 1960 $120,000 18 DEC's first computer PDP-2 NA 24 Never built? PDP-3 36 One was built by a customer, none by DEC. PDP-4 1962 18 Predecessor of the PDP-7. PDP-5 1963 $27,000 12 The ancestor of the PDP-8. PDP-6 1964 $120,000 36 A big computer; 23 built, most for MIT. PDP-7 1965 ~$60,000 18 Widely used for real-time control. PDP-8 1965 $18,500 12 The smallest and least expensive PDP. PDP-9 1966 $35,000 18 An upgrade of the PDP-7. PDP-10 1967 $186,500 36 A PDP-6 successor, great for timesharing. PDP-11 1970 $10,800 16 DEC's first and only 16 bit computer. PDP-12 1969 $27,900 12 A PDP-8 relative. PDP-13 NA Bad luck, there was no such machine. PDP-14 A ROM-based programmable controller. PDP-15 1970 $16,500 18 A TTL upgrade of the PDP-9. PDP-16 1972 $.8-$4,000 NA 8/16 A register-transfer module system. Corrections and additions to this list are welcome! The prices given are for minimal systems in the year the machine was first introduced. The bits column indicates the word size. Note that the DEC PDP-10 became the DECSYSTEM-20 as a result of marketing considerations, and DEC's VAX series of began as the Virtual Address eXtension of the never-produced PDP-11/78. It is worth mentioning that it is generally accepted that the Data General Nova was originally developed as the PDP-X, a 16-bit multi-register version of the PDP-8. A prototype PDP-X was built at DEC before the design was rejected. This and a competing 16-bit design were apparently submitted to Harold McFarland at Carnegie-Mellon University for evaluation; McFarland (and perhaps Gordon Bell, who was at C-MU at the time) evaluated the competing designs and rejected both in favor of what we know as the PDP-11. (A less common version of this story is that the reason that DEC never produced a PDP-13 was because the number 11 was assigned to what became the Nova; this is unlikely because the PDP-X prototype came before the PDP-11.) Both DEC and Data General are quiet about these stories. Today, all of the PDP machines are in DEC's corporate past, with the exception of the PDP-11 family of minicomputers and microprocessors. Of course, occasionally, some lab builds a machine out of DEC hardware and calls it a PDP with a new number. For example, the Australian Atomic Energy Commission once upgraded a PDP-7 by adding a PDP-15 on the side; they called the result a PDP-22. See Mark Crispin's 1986 list of PDP's elsewhere in this document. ======================================================== What is a PDP-11? Evolution of the PDP-11 family of computers. During the late 1960s DEC had built a successful business based mainly on the success of its 12-bit PDP-8 series of minicomputers. However, the time had come for the introduction of a 16-bit machine to replace/supercede the -8. Edison DeCastro designed a 16-bit machine, but after a disagreement left DEC, formed DG, and built the initial success of that company on his 16-bit NOVA. There was much rancor surrounding the events of DeCastro leaving DEC and setting up DG. Stories abound as to the reasons of the bitterness, but I have never been able to get an authoritative source to confirm what really happened. DEC eventually countered with its entry into this market segment - the PDP 11/20. This machine was to father a whole industry; lay the foundations on which the VAX would later be built; and virtually launch the OEM industry attracted to the connectability and extendability of the UNIBUS, and later, Q-Bus. Indeed, Computer Engineering by Bell/Munge/McMcNamara refers to the VAX-11/780 as being another -11 rather than the start of a new and different family. The early VAXes, of course, had PDP-11 compatability mode built in, and many VMS utilities were taken from RSX and run in compatability mode for a number of years until eventually replaced by native mode utilities sometime around VMS V3.0. Since then, the PDP-11 had 16 to 22 implementations, depending on how you count them, many with variants. The following attempts to briefly track the evolution and progression. In 1969 the -11 family was projected as follows: Model CPU Comments ------ ----- ---------------------------------------- 11/20 KA11 Origin of the species 1x performance. 11/10 - .7 of the 11/20, technologically cost reduced 11/20 in MOS. [This obviously became the 11/05, 11/10] 11/30 KA11 [Seems to have been the same as an 11/20 packaged with a little more memory, etc. I believe this is what eventually became the 11/20 that actually shipped] 11/40 KB11 2x performance. 11/45 KB11 2x performance. [Seems to have been intended to be an 11/40 with MMU. [Looks like this became the 11/40 that eventually shipped.] 11/50 KC11 2x performance. Hardware floating point 32 bit processor. [I believe the 32 bit refers to the FPU!] 11/55 KC11 2x performance. With MMU. [It looks like the 11/50 plus 11/55 became the eventual 11/45] 11/65 KD11 4x performance. 32 bit seperate memory bus, 32 bit processor. It is interesting to note how things progressed in reality. Technology allowed, and the market drove, the production, within a couple of years, of machines considerably in advance of what was envisaged on April 3 1969. It is also interesting to note that some people were already thinking 32 bits! ======================================================== What different PDP-11 models were made? - Jun 1970: 11/20, 11/15 born. Small Scale integration. 4 or 8k words mem, 28k max. (Some documentation referred to 32k max memory, but the top 4k was reserved for the I/O space. Machines with 28 KW core were rare, and most were shipped with 4 KW or 8 KW). Magnetic Core Memory. TTY ASR33 console. Papertape reader/punch typical I/O. Clock State cpu control. [All subsequent PDP-11 machines were to be microcoded]. The processor boards, all 15 of them (plus an optional line time clock, KW11-A), plugged into a 3 bank 4 x 6 slot backplane. Each 4 KW of memory occupied a further 4 x 6 slot backplane with some 12 modules. There was room in the 11" CPU drawer for three such additional backplanes. The MM11-E 4 KW memory module took 1.2us for a full memory cycle. Q: Why does the 11/20 have 18 bit addresses on the UNIBUS but only a CPU capable of handling 16 address bits? A: Because it was always intended to provide an MMU option to allow for extended addressing. No matter what memory configurations, 16 bit, 18 bit or 22 bit were to be employed throughout the life of the PDP-11 family, the top 8 KB were always reserved for I/O addresses, registers, etc. In particular (initial list provided by Megan Gentry): - The I/O page is 8 KB standard - Some systems (PDT) have 4 KB I/O pages - Some systems can be configured for 4 KB I/O pages - There is a quirk in the memory management units which cause the microcode to assume an 8 KB I/O page regardless of the jumper configuration - so, if you have a system configured for a 4 KB I/O page and turn on the memory management unit, the system will suddenly think it has an 8 KB I/O page. This can cause, for example, RT-11XM to go south really quickly. A possibly-related feature is that, after reset, the memory map has kernel memory corresponding to low physical addresses for the first seven segments, and the last segment pointing at -8KB. This was to allow bootstrap programs to easily access device registers without needing to know about memory management. - The address of the I/O page (8 KB) is, on 16-bit systems, 160000. On 18-bit systems, 760000. And on 22-bit systems, 17760000. - Jun 1972 11/45. This was the first of the highspeed processors that begat 11/50, 11/55 and 11/70. 11/45 was microcoded, SSI/MSI, memory bus, core, MOS or bipolar memory. Max Memory 256 KB addressable via optional 18 bit Memory management unit. Optional Floating Point Unit. 11/55 had special bipolar high speed mem. Fast peripheral to memory slots Split I&D spaces. Introduced some extra instructions such as MUL, DIV, ASH, ASHC, SPL. The 11/45, /50 and /55 had the same CPU - the differences being in memory types, bus layouts, etc. The 11/70 was to have essentially the same cpu, with modifications to allow for Cache, 22-bit addressing and, for the first time, non-Unibus memory. The PDP-11/45/50/55 had two Unibuses, normally joined by a single spaced jumper. The second Unibus has no arbitration, and was part of dual-ported fastbus memory. If you had fastbus memory (which made a 45 a 50 or 55), a second processor could access the memory. The only problem was that with the Unibus A and B split, DMA devices on Unibus A could not see the fastbus memory. I [not MMcC] had a PDP11/50 and PDP11/20 set up in such a fashion, with the PDP11/20 doing high speed A/D sampling and signal averaging using shared memory with the PDP11/50. The fastbus memory is an independent high speed data bus internal to the 11/45 xx processors, with up to two solid state memory controllers and had each controller had two ports one for the CPU and the other available for a second Unibus where concievably a high speed DMA device could directly write to the memory. The DMA device on the `second' bus had to have a Unibus priority arbitration system, so you could in fact connect another CPU to it a bit like the DTS07's in concept. Note that, just to confuse the issue, this is not the same as the product/feature later marketed as FASTBUS. KB-11 was the original /45 cpu, and used the FP-11 asynchronous FPP. Later machines under the /45 label were core memory /55s. - Jan 1973 11/40, 11/35. Price same as 11/20, higher performance. (See tables and chart below for relative performance of the various PDP-11 processors) Small- and Medium-Scale Integration. Architecture of CPU like 11/45 without the raw power. Memory Management Unit, EIS/FIS Extended and Floating instruction sets as options. Introduced with Core memory, and later with MOS. Microcoded. Max Memory 256 KB. Extra instructions such as SOB XOR MARK SXT and RTT introduced. MUL, DIV etc implemented in the EIS option. - Jun 1972 11/05, 11/10. Performance same as 11/20, lower price. Microcoded. 2-board processor. New 8 KW 3-board core memories were introduced with the /05 and /40. Later on, 16 KW memories were used before core got supplanted my MOS Memory. I remember these memories spec'd for a 980ns read/write cycle. I also remember the 11/05 CPU boards having the most green ECO wires I had ever seen on a machine. The cost of adding those wires manually must have, on reflection, added significantly to the cost of manufacture of the 11/05. Later board revisions eliminated these almost completely. It is interesting to consider that modern design, simulation and testing tools has virtually eliminated the ECO wire practice - a practice that we took for granted during the '70s and early '80s. The /05 front panel has the following control switches: LOAD ADRS EXAM CONT ENABLE/ START DEP HALT When HALTed, the CONTinue key performed a single instruction per key depression (as do all the other 11's with front panels.) There is a single 16 bit ADDR/DATA multiplexed display and a single RUN status light. The power switch has the following positions : OFF / POWER / PANEL LOCK. - Mar 1975 11/70. CPU very similar to 11/45 in raw performance. Machine introduced with had core initially and MOS later. These machines introduced Cache, 22-bit Memory management of up to 4 MB. Optional Floating point processors. Massbus periperal controllers which had a direct path to memory first appeared on this machine. Note that MASSBUS (RH70's) adapters attached directly to memory were unique to the 11/70 -- MBAs only otherwise appeared on different series (PDP-10, VAX etc). Unibus systems could use MASSBUS peripherals, but the controllers (RH11's) spoke over the Unibus and lost most of the speed advantage. While this machine was not the fastest -11 (that title belongs to the bipolar memory equipped 11/55), no other -11 could approach the 11/70 in terms of I/O throughput over its multiple massbus/memory bus architecture. The KB-11B was the original 70 cpu. Similar to the KB11 based 11/45, plus unbus map, 22-bit, MBCs etc. The 11/70 had the `feature' of the slowest bus of ANY -11. And when a UNIBUS peripheral did DMA, EVERYTHING stopped! This is one of the reasons the Seti upgrades are so good. They enable the RHs, CPU, and UNIBUS to all operate in parellel. KB-11C: The FP-11 proved `featureful' in practice, and was replaced with a faster synchronous FP-11C. This required the `FP-11C compatible KB-11.' The 11/70 was a 18 month overnight wonder to fill the gap left by the late development of the 32-bit wonder box! :-) The C/D cpus used the FP-11C FPP. In fact, the KB-11C is referred to as the `FP-11C compatible KB-11' in some manuals. - Relative CPU performance: 0.60 (VAX780 = 1.0) - Technology: SSI/MSI TTL - I/O Bus Capacity: 4 MASSBUS ports - Space Requirements: 9.0 square feet (2 H960) - Power Requirements: 6,000W - 1975 (ish) LSI-11, first of the microprocessor -11s, implemented on 4 chips. It was sold by Western Digital as the WDC-16. First of the Q-bus machines (All others above were UNIBUS). Implemented on a single quad height board. Performance approximately equalled that of the 11/05. Minimal size. Aimed at OEM embedded controllers, etc. - Jun 1975 11/03 Same microprocessor as 11/2. Performance the same as the 11/05, but priced much less. Qbus. More expandable than LSI-11/2. Aimed at low end of 11/05 market. - Sep 1975 11/04. UNIBUS. There are conflicting reports about this model. One is that it was a replacement for the 11/05, with the same performance, but priced much less. Standard TTL and STTL logic. It only used one cpu board instead of the 11/05's two. The other version is that it was a "reduced" version of the 11/34, with 16-bit addressing, no cache, no FPP option, etc. It was designed by the same person as the /34, and it fitted on one UNIBUS board. Apparently introduced in 1978? - Mar 1976 11/34. Follow-on to 11/40 with same performance at lower cost. Two board cpu in SSI/MSI TTL. Initially had a two-switch KY11-LA front panel (Halt&Boot). Optional calculator-style Octal KY11-LB front panel later, although most customers opted to have this as time progressed. The KY11-LB could be used to singlestep or microstep a program for diagnostic use. The /34 style memory managment was 18 bit and the memory management was standard. - Jun 1976 11/55 had special high speed (300 ns) bipolar mem. Floating point as option. Dual register set, as well as Kernel, Supervisor and User CPU operating modes as on the 11/45, 11/50, and (later) 11/70. Interestingly, a table in Bell/Mudge/McNamara's Computer Engineering (page 406) shows the 11/55 performance relative to the 11/03 for basic instructions per second as 41 (vs 36 for the /70) and Whetstones of 725 (vs 671 for the /70). Obviously the 300 ns bipolar memory made a difference in raw performance. Of course this system could not approach the /70 in throughput. KB-11D The 18 bit version of the C. used in /55s and very late /45s. I think all /50s were KB-11 cpu's. (PaulR) The big difference between a /50 and a /55 is the /55 is a KB-11D, not a KB-11 cpu: - KB-11: 11/45, 11/50 - KB-11B: 11/70 - KB-11C: 11/70 - KB-11D: 11/55 - KB-11Cm: 11/74* - KB-11E: 11/74* that never shipped. * See the Never 11's section. - 1976 (ish) LSI-11/2 (11/21?) KD11-HA. Double height module follow-on to LSI-11. Performance of an 11/05, but priced much less. Qbus. Lacks onboard memory and WCS chip socket. Basically the same chipset. Both used in PDP-11/03 systems. LSI-11 sucks more power than the LSI-11/2. The LSI-11/2 chipset was simply "the LSI-11 chipset," manufactured by WDC for DEC. FIS/EIS upgrade microms (MICrocode ROMS) were available for the LSI-11, and at least on the PDT-11s there was a special 2-in-1 version of the regular CPU microms that would free up a socket for the FIS/EIS microm. - Jun 1977 11/60. Intended follow-on to 11/40 at the high end/same price. Higher performance. Writable control store for custom instructions. Cache and ECC MOS memory. Too costly, too late. Memory management was 18 bit and standard. Floating point instructions were standard - but implemented by the CPU microcode. There was a floating point coprocessor option. The 60 was to have been a 22 bitter originally. - Mar 1978 11/34a, 11/34c. The /34a with the "right cache" presented a higher level of performance than the then "hot machine" of the time - I believe it was the /60 - in the eyes of -11 engineering / central engineering. The "c" upgrade was the re-establishment of the original cache. Thus, the /34c was an internal mythical model to allow FS to keep track of what systems had the upgrade - much like the /35 vs /40 clock mod that made the /35 faster. - 1978? PDT family. PDT 11/110, 11/130, 11/150. The PDT-11/110 and -11/130 were built into the cardcage of a VT100 (along with the terminal). The 11/110 simply had code to allow down-loading of the PDP-11. It had no peripherals. The 11/130 had two TU58's mounted just under the monitor. The PDT-11/150 was built into a table-top unit which also had two RX01 equivalent drives, and the cpu board was built into the the Floppy box. The PDT-150 had separate VT100 and systems box. The system box for the single disk unit: 51.0 cm (20.08 in) length X 33.02 cm (13.0) width X 20.9 cm (8.23 in) height and 33 pounds. Dual disk unit: same, but 34.8 cm (13.42 in) height and 46 pounds. The box slopes to the front and has a small front panel that reads `digital PDT-11' and has four LEDs ("1", "2", "RUN", "POWER"). LED 1 Lights to indicate a system error when in the self-test mode. LED 2 lights to indicate that the system is waiting for an autobaud response from the console terminal. Otherwise both can be controlled by a user program. The top of the case is plastic and is held fast by two screws; undoing these allows access to the CPU and logic. Two RX01 drives (8.5" floppies) are mounted in the bottom 75% of the cabinet. There are three terminal ports, one console port, one printer port, and one modem port. The 3 terminal ports are optional. All of the connectors, save for the modem port, are female DB25 connectors, which I have been told is rare. Depending upon the version of RT-11 being used, the machine expects either VT52 or VT100 console/terminal input -- I believe that versions prior to 4.0 default to VT52. The stock memory appears to be about 30K words (not including the I/O page). It is also noteworthy that the RX01 firmware is suspected of not being strictly "real" RX01. The PDT will write fresh single-density formatting every time it writes to the disk. It's also interesting to note that the physical device name for the drives is PD: instead of DX: The documentation calls the drive controller an RXT-11. It also claims that a PDP11/V03 with RXV11 is compatible with the PDT11/150. The print set shows 27 sectors/track for the PDT. The RX02 User's Guide shows 26 sec./trk. All three PDT's had the equivalent of an 11/2 (same chip set, in fact) and 60 KB addressable (rather than 56 KB, since it had only a 4 KB I/O page) These machines, running RT11, could be viewed as being the forerunners of today's PCs. They were never marketed as such, and thus faded into obscurity. Although there is no I/O bus, per se, the print set gives the controller card equivalent for the on-board circuits: - Console Terminal: DLV11-A - Asynchronous Comm Port: DLV11-E - Printer: LAV11 - Cluster Controller: DLV11-A - Floppy Disk Port: RXT-11/RX01 - Line Time Clock: KW11-L - Synchronous Comm: DUV11 A useful table from the PDT-11/150 User Guide: PDT-11/15x-yz x is console terminal: 0 NONE 1 VT100-AA, VT100-AB 2 LA120-AA, LA120-BA, LA120-DA 3 LA34-DA, LA34-HA 4 LS210-HE, LS210-HJ 5 LA36-HE, LA36-HJ - 1980 (ish) 11/44. Successful follow-on to 11/40 high end/11/70 low end. Almost 11/70 power at 11/40 price. UNIBUS. Also, it could have the CIS option. The front-end processor on this system was built around the Intel 8085. Lacked the dual register set of the 11/70. - Relative CPU performance: 0.42 (VAX780 = 1.0) - Technology: SCHOTTKY TTL MSI - Maximum memory: 4 MB ECC MOS - Maximum I/O throughput: 5 MB/s UNIBUS - Cache size: 8 KB - Cache Cycle time: 275 ns - Space requirements: 4.4 square feet (H9642) - Space requirements: 6.3 square feet (H9645) - Power requirements: 1,224W - 1979 11/23. Successful follow-on to 11/03. Single F(onz)-11 chip. 11/34-ish performance at lower cost. Qbus. F11 chip does 22 bit addressing, but only 18 address lines brought out in earliest versions; all 22 brought out on later revs of the KDF11-A. - 1980 (ish) 11/24. successful follow-on to 11/04, 11/34. F-11 (Fonz) chip. Price of 11/04, performance of 11/34. The 11/23 and /24 had the 11/34 style memory management. They both had 22 bit addressing, but for the /24, the UNIBUS map (to map 18-bit UNIBUS DMA addresses onto the 22 bit memory address) was a (rather rare) option called, I believe, a KT24. - 1983(ish) The T-11 (Tiny) is a similar architecture to the LSI-11 on a single 40-pin DIP that was primarily intended for the embedded market. It was used only in the Falcon SBC-11/21 and a few controllers (e.g. RQDX3, DEUNA, LA-120). The T-11 was also used in the KXT11-CA Quad width `communications processors' that allowed you to have multiple CPU's on the Qbus. One cancelled DEC project used it as a cpu/controller inside a telephone (with keyboard, video, etc). - 1984(ish) PRO-350, PRO-325. This machine was released as one of a triumvirate of PCs by DEC. The PCs consisted of the DECmate-II PDP-8/WPS based dedicated word processor; the 8080/8086 based Rainbow, and the F-11 based PRO-325/350. Although the machines were well engineered, they were not successful in the marketplace for a number of reasons. First, the customer base was confused by being offered three totally separate, incompatible offerings. Second, the Rainbow, although able to run both CP/M and MS/DOS, was incompatible in both hardware and software with the IBM PC that was establishing the defacto standards for the industry. And third, the PRO-350 was based on a bounded, restricted version of RSX11, and was viewed as an oddity in the marketplace. The PRO-325 was the same as a PRO-350, but it only had the RX50's in it; the PRO-350 also had an RD-series hard drive (originally an RD50, but with newer controllers you could have up to an RD52). The PRO-380 was the same as the PRO-350 with respect to devices. All three had a bitmap display. The PRO-325/350 was based on the F-11 (11/23) chip set. The PRO-380 was based on the J-11 (Jaws, 11/73) chip. They all were desktop units, though an option allowed them to be mounted in a tower configuration. Note on the Pro 380: one reason for its failure was its bad performance. It ran the J-11 at only 10 MHz. Reason was a design mistake: the entire system has only one clock, 20 MHz, for everything from CPU to video to UART baud rates. J-11 was planned to do 20 MHz, fab only got it to 18, but the design didn't allow for a separate CPU clock so the Pro had to go all the way down to 10. - 1986(ish?) PRO-380. This was an upgrade to the PRO-350, using the J-11 chipset. The market opportunity was closed to it at this time, and they only had limited success. The PRO-350/380 probably saw most use as console devices/frontends for a number of the VAX8000 series machines. In the following sections, quotes marked [-PSH] are extracts from the 1987 "PDP-11 Systems Handbook" - early 1980s 11/73, Follow-on to 11/23, 11/24. J(aws)-11 chip. Similar cost, higher performance. Replacement for 11/44. The MicroPDP-11/73 computer provides one-third more compute power than the MicroPDP-11/53, ... 15-megahertz J-11 chip ... Memory is expandable in 1- and 2-Mbyte increments .... [-PSH] 11/73 is the KDJ11-A or KDJ11-B. (The -B just puts things like the console SLU and boot roms onto one board; some revs also have PMI memory ... the boundary between the 11/73 and 11/83 is a bit fuzzy...). There was never a UNIBUS equivalent of the /73. The /73 didn't replace either the /44 or the /70. (Nothing replaced the 11/70! Nothing else had the I/O throughput, and the CPU was only just outrun by the 11/83 / 11/84.) - 1985-1986 11/83, 11/84 Higher performance versions of 11/73. The computing power of the MicroPDP-11/83 has twice the performance of the MicroPDP-11/73 .... The MicroPDP-11/83, by combining an 18-megahertz J-11 chip and a companion floating-point accelerator chip with a new private memory interconnect on one module, .... [-PSH]. The MicroPDP-11s (11/23+, /73 and /83) were in a tower configuration which could be configured for desktop use, or the innards removed and rack-mounted. (The differences between the /73 and the /83 were simply: - The board clock speed, 15 MHz vs 18 MHz (some /83s ran at 15MHz, though) - the type of memory. The 11/83 had PMI memory which was configured before it on the Qbus. The 11/8x can't go much above 18 MHz. While the original design called for 20 MHz, neither the J11's nor the gate arrays were up to it. They use Private Memory Interconnect (PMI) much like the 11/70 did years earlier. The memory (for the /83) lives in the usual PMI slots, and then a bus adapter brings the bus out to the UNIBUS. DEC realized that they had a lot of customers with UNIBUS peripherals, but they didn't want to build another UNIBUS processor (the previous one being the 11/24), so they expanded on the 11/24 + KT-24 concept and came up with the 11/84. It was mostly UNIBUS, but the first slots were QBUS (so it could use the KDJ11-B boards used in the 11/83), followed by a QBUS-UNIBUS adaptor. Considering that at that time, all DEC had on the Qbus was the RD-series and the KDA50 which started out as a real power pig, UNIBUS was the way to go if you wanted a system with big (but genuine DEC) disks and high-end tapes. An alternate viewpoint from Don Stokes: I'm not sure I agree re the peripherals for the 11/8x and onward. The KDA50 was a pig, but so was the UDA50, and by then DEC weren't selling anything but RAxx drives as "big" disks. Tapes were always a problem, but the TU81 was available by the mid 80s, and the TS05 was also available. I got the distinct feeling that the 11/84 was aimed at upgrades and additions for sites with a heavy UNIBUS investment rather than for new systems/sites. After all, burst mode made the Qbus faster than the UNIBUS, the boxes were smaller and much less power hungry. (KDA50 notwithstanding -- KDA50s inevitably got put in an expansion chassis because of the power. But at least the expansion box could hold 5.25" drives as well.) I never could understand why DEC abandoned dedicated peripheral controllers in favour of the UDA50. We used to get much more throughput (commercial loads) out of 11/70s with RP06s and RM05s than we ever could with RA81/UDA50 equipped 11/750s running the same applications. 11/44s seemed similarly handicapped. - Relative CPU performance: 0.72 (VAX780 = 1.0) - Technology: J-11 18 MHz Chipset MSI/LSI - Maximum memory: 4 MB PMI ECC MOS - Bus Capacity: 5 MB/s UNIBUS - FPA standard, FPP standard - Cache: 8 KB - Space Requirements: 6.2 square feet (H9642) - Power Requirements: 1,100W - 1987(?) 11/53. Essentially a stripped down /73. KDJ11-D I think -- J11 chip, 15MHz, lacked cache or FPA options, has (slowish) onboard memory. There wasn't a /54. The heart of the MicroPDP-11/53 is a 15-megahertz, J-11 single board computer with 0.5 Mbytes of onboard memory ... The MicroPDP-11/53 PLUS supermicrosystem ... has an additional 1 Mbyte of memory for a total of 1.5 Mbytes of onboard memory. [-PSH] - 1990 11/93, 11/94 Possibly the last PDP, they're just the 83/84 CPU board with a higher clock speed. The 11/93 and /94 are a new design which uses the J11 CPU. Instead of cache, the entire main memory (2 or 4 MB) is on-board w/ 70 ns parts. A new memory controller gate array lets the CPU at the memory during NPR transfers (even during block mode). A Z80 CPU controls 8 emulated DL ports (this subsystem is called a DLV22) with buffering, etc. The board uses the same 18 MHz DCJ11-AE as the 11/8x - all the speed improvements are from a more modern board design. The 11/9x will go above 18 MHz. DEC marketing material: Product Description The PDP-11/94 is the newest and most powerful member of the PDP-11 family of multiuser systems. The PDP-11/94 features a new, performance-enhanced processor that combines the DCJ11/FPJ11 chip sets with 2 Mbyte or 4 Mbyte of high-speed onboard memory, eight buffered, programmable asynchronous serial lines and a time of year clock. The single-board implementation of the processor effectively complements the configuration flexibility and expansion capacity of enhanced UNIBUS systems packaging. FEATURES - A new performance-enhanced single-board CPU features Digital's C-MOS 18 MHz J-11 chipset, FPJ-11 coprocessor, parity memory, and eight buffered serial lines - The full PDP-11 instruction set including floating-point and EIS instructions, plus an integral floating-point coprocessor - Sophisticated 22-bit memory management, dual register set, separate instruction and data space, and three system modes: kernel, supervisor, and user - 2 or 4 Mbyte of onboard high-density parity memory - Private Memory Interconnect (PMI) architecture for high-speed data transfers and enhanced system performance - 64 Kbyte bootstrap/diagnostic ROM facility and 8-Kbyte EEPROM (100% diagnostic coverage) - Program-controlled line-frequency clock - Eight-line buffered programmable EIA/CCITT serial-line asynchronous interface - ASCII console logic for system control and debugging - Time of year clock - Full battery backup support available - Concurrent processing that allows the simultaneous execution of instructions and DMA transfers - New compact design that requires less power and offers more expansion capacity and configuration flexibility - Consistent UNIBUS systems packaging: standard 10.5 inch by 19 inch rackmount design center, H9642- and H9645-based systems cabinets - Board-Level upgrade packages for installed PDP-11/84s ======================================================== What Did a PDP-11 Cost? Here are various marketing price books and such, to give an idea of what the original retail price of a new PDP-11 was. Note that the images listed in each book are scans of the actual pages, and so tend to be large (usually in the 700-1000KB range). For those reading this as a simple text file, all of the images are available at ftp.village.org in the directory: /pub/pdp-11/faq.pages/price.images - Price List for IDACS-11 in August 1971 - Price List for PDP-11/05 and /15 OEM in April 1972 - Price List for PDP-11/20 in April 1972 - Price List for PDP-11/20 in August 1971 - Recommended Spare Parts for PDP-11/20, June 1970 - Price List for PDP-11r20 in May 1971 ======================================================== Differences between the 11/70 and the 11/83, 11/93 Here's an excerpt from an old Micronote (#039) (Thanks Richard Wallace) +---------------+ +-----------------+ | d i g i t a l | | uNOTE # 039 | +---------------+ +-----------------+ +----------------------------------------------------+-----------------+ | Title: Differences between KDJ11-A and KDJ11-B | Date: 8-Aug-85 | +----------------------------------------------------+-----------------+ | Originator: Peter Kent | Page 1 of 5 | +----------------------------------------------------+-----------------+ Purpose The purpose of this MicroNote is to identify and discuss the differences between the KDJ11-A and KDJ11-B CPU modules. [ Stuff Deleted ] Cache For a full discussion of cache memory as used on the KJD11-A and KDJ11-B refer to MicroNote #9 and the KDJ11-A and KDJ11-B User's Guides. Both CPU modules have a similar cache organization using a nine bit tag. This nine bit field contains information that is compared to the address label, which is part of the physical address. When the physical address is generated, the address label is compared to the tag field. If there is a match it can be considered a hit provided that there is entry validation and no parity errors. The KDJ11-B has an additional tag store called the DMA tag. The DMA tag is an identical copy of the cache tag store and is used to monitor the main memory DMA updates while the cache tag store monitors the DCJ11 requirements. The presence of the second tag store - DMA tag - allows the J-11 microprocessor to continue processing after it has relinquished the system bus to a DMA device. When the DMA tag detects a hit (main memory location written to by the DMA device), the microprocessor stops and relinquishes the internal bus to the cache controller to allow it to monitor further DMA activity on the bus. The KDJ11-A, however, has only one tag store and stops processing as soon as it relinquishes the system bus to a DMA device. The PDP-11 processors have also found themselves in other roles: - Most PDP-10/DECsystem-10 and DECsystem-20 frontend processors and communications processors were PDP-11/20s and /40s. - VAX-11/780 front end processor/console was an 11/03. - Many of the VAX 8000-series machines had PDP-11 based PRO-350/380 frontends. - LAT was originally implemented on PDP-11s as comms processors. - DECSA Ethernet Terminal Server had a PDP-11 as a heart. - All the HSCxxx Storage controllers use PDP-11 processors. - DEUNA Ethernet Controller. ...and elsewhere. ======================================================== Other fun PDP11's The 11/10S. This was a 11/10 CPU (basic instruction set, no memory management; a low-end PDP11), with the interesting feature that you could disable the bus arbitor, and it became a DMA peripheral to another PDP11. In other words, a parallel processor. I have never seen this documented, but the boards were common enough as simple 11/10 processors. ======================================================== The Never 11's There are a number of very significant projects that never came to market as originally envisioned, although the lessons learned sometimes got applied to later offerings. - Hydra Was to have used the KB-11Cm CPU modified to interlock the ASRB instruction in memory, allow cache bypassing on a per page basis, and tweaked powerfail/re-start for the 11/74. These were shipped with MKA-11 memory boxes as the 11/70mu system, all to AT&T, I believe. The only multiprocessing systems were Castor/Pollux in the RSX development group in ZK (Software Engineering at Spitbrook Road, Nashua NH), and the RSX DECnet group in Tewksbury MA. Ontario Hydro also had one for field test and invented "just say no" when the field test ended. :-) BTW, HRC, the reconfiguration task, is short for "Hercules", who tamed Cerberus (the MP version of TRAX/M-PLUS). - 11/74 Probably the most famous PDP-11 that never was. Designed as a 4-way multiprocessor with four 11/70 processors clustered around shared memory. Configuration was SMP. Furthermore, the processors, which had been originally designed as FORTRAN crunchers, were to be equipped with the Commercial Instruction Set (CIS) for Cobol applications. Prototypes were built and a number of alpha units installed, but the product never came to market. Reasons for it never being shipped are various and may be apocryphal: the backplane would have been so complex to be almost unmanufacturable; the cost due to the complex backplane would have been too high; the 11/74 with CIS would have blown the new VAX-11/780 out of the water in commercial applications. Those that truly know are not talking :-) The backplanes are almost standard KB-11C. The microcode is changed to interlock the ASRB instruction, cache bypassing is added and a few other minor changes. No problem to manufacture. The memory is the MKA-11, with 4 memory ports. That's 32 flat gray cables in and out of each box except the last, plus 4 box controller cables and battery backup. The CIS equipped unit was the KB-11E cpu, aka 11/110. Another contempory of these was the 11/68. (see Bluefin) There's also the IIST, the DIP-11, and so on, for which no useful information has been found to include in this FAQ. Robert Boers reports: I was in DEC Engineering for more than 20 years. One piece of data I can add: The reason that the 11/74 was never produced was not related to competition with the 11/780. The reason was that Field Service wanted an exorbitant upfront amount from Engineering, if they had to lower the yearly maintenance fee for the 11/74 to a 'normal' % of the purchase price (around 10% if I remember correctly). DEC produced a few 100 of the 11/74, which were mainly used internally. I remember that they were quite reliable. I believe we had some near my office with a dual CPU, but I don't recall ever seen one in use with 4. - KB-11E This was to have been the `real' /74. A KB-11Cm, cleaned up, and with CIS included. Canned just as it was to go into production. The maintenance prints for the CIS were in the hardware catalogue, as were the MKA-11 manuals. The KB-11Cm tech manual is listed as EK-KB11CM-TM, yep 2-6-2 not 2-5-2, in at least 2 places (see the Part Number Format section). - Bluefin, aka 11/68 The /60 was to have been a 22 bitter originally. The 11/68 was to have had up to 16 cpus, each as powerful as a 4-cpu /74. Canned to prevent competition with a future 32 bit product. - ECL-11 18 bit system done at CMU. - 11/110 and 11/120 The MKA-11 manuals refer to these. Perhaps they were going to be what became the 11/780 VAX? ======================================================== Non-DEC 11's Soviet PDPs The PDP-11, as the PDP-8 before it, was cloned and copied extensively behind the so-called Iron Curtain. A number of plants produced PDP-11 compatible systems in the Soviet Union, including Elektronika-79 (11/70) and several machines without direct DEC analogues (DWK-4 with proprietary video controller). I've never seen CIS realised on any Soviet-built clone. Elektronika-85 (Professional-350) was the most popular Soviet PC (of very low quality, though). PDT-based IBM PC killer Reported by Jerome Fine: With respect to the different models of the PDP-11, your lists mention the PDT models which has a QBus backplane within a VT100. One model that I saw which was custom built included an 11/73 dual (KBJ11-A) along with a DLV11-J for ports. The memory used was a Cristlin 4 MByte quad board (some bright individual must have modified the backplane with a magnifying glass and added the wires to bring it up to 22 bits). The disk drive was an RD53, but it used a third party disk controller from SIGMA. Finally, they had also added a DHV11 to get an additional 8 serial ports. Except for the third party controller (an RQDX3 has no boot roms - also the memory could have used the MSV11-QC), all of the components were from DEC. They had stuck the disk drive under the video tube (evidently it was a real squeeze) with cables out the back to add a second drive. Does this example qualify for mention? It certainly was a power house and would have been the best scope on a PC if DEC had ever decided to put that much power inside the lowly VT100 as a standard. ======================================================== PDP-11s behind the Iron Curtain The PDP-11, as the PDP-8 before it, was cloned and copied extensively behind the so-called Iron Curtain. A number of plants produced PDP-11 compatible systems in the Soviet Union, including Elektronika-79 (11/70) and several machines without direct DEC analogues (DWK-4 with proprietary video controller). Nobody knows how much of these clones were issued by many of the plants in the countries of the Warsaw Pact, but I believe that the total amounts of units should counted by hundreds of thousands. AFAIK the following countries issued a DEC clones of computers and peripherals: - Soviet Union (SM-4, SM-1420/xxx, SM-1600/xxx, Electronika-xxx, DWK-n, UKNC,...) - Bulgaria (SM-4, SM-1420/xxx) - Eastern Germany "DDR" (SM-1420/xxx) - Poland (Mera-xxx) - Hungary (SM-4) - Note that `SM' appears as `CM' in Cyrillic (see discussion below regarding Cyrillic letter usage on this page) Not all clones had analogues at DEC product line, but most of them were very close to some model (not in quality though). All DEC software and Unixes runs on these computers without problems (in fact, Soviet users used adopted versions of software because the KGB stole ALL source codes for RT11 and RSX11 and made it freely distributed; after a while it was modified to have support for Russian language and some nonstandard devices/architectures, RT11 became RAFOS, FOBOS, and FODOS, and RSX11 became OSRV). Computers We can divide the clones into four categories: - - UNIBUS - - QBus with LSI-11 - - QBus with Single chip CPU - - Proprietary bus Below is the list of clones we know of so far: - MINICOMPUTERS - * SM-3 UNIBUS. 11/05 clone. There's some argument that better be described as a microcoded 11/20. Eventually, someone will have to sit down with the English and Russian spec sheets and cross-match to determine the best description... - * SM-4 UNIBUS. Produced in SU and most other Warsaw Pact countries. Analog of the 11/40. most had core memory. - * SM-1420/xxx (SM-1420/xxx, SM-1600/xxx, Elektronika 100/xx, Mera-xxx) UNIBUS. Most popular models, analogues of 11/34-/55 depending on the "xxx" (even 11/74 extensions) and had lots of options. Based on bit-slice processors. - * TPA-11/40 UNIBUS. From Hungary. Direct PDP-11/40 clone. - * TPA-11/48 UNIBUS. An enhanced TPA-11/40. The enhancements included 22 bit maps, split I/D, cache, etc, so that it looked enough like an 11/70 to fool DEC OSes. Ran much more slowly than a real 11/70 (actually, the 11/48 was slower than a TAP-11/40). No MASSBUS (on any TPA model?). - * TPA-11/110 aka TPA-Janus. From Hungary. A multi-processor machine, with a Russian Elektronika-MC1201.01 CPU (LSI-11 clone) and a Z80 as secondary processor. There could be 2 or 3 Z80s on the QBUS. - - MICROCOMPUTERS - * Electronica-60 QBus/LSI. Very popular microcomputer in the beginning of 80's VERY similar to the original LSI-11. - * DWK-n line Single chip CPU (K1801BMx), QBus. Most popular computer of the 80's ranged from DWK-1 to 4. - DWK-1 - PDT 11/130. - DWK-2 - PDT 11/150. - DWK-3 had an 1801BM2 CPU with the same features as DWK-1/2 (technically, a DWK-2M) plus a built-in MMU and was equipped with a proprietary black&white graphical display and two floppies (each 200KB, 40 tracks, single-sided). No direct DEC analogue. - DWK-3M was a DWK-3 with 400KB floppies (80 tracks, 10 sectors, double-sided), a 10MB CM5508 hard disk (made in Bulgaria). Later models have a color graphics controller. - DWK-4 had a EIS/FIS enhanced CPU (1801BM3), 1MB of memory, a 20MB hard disk (MC5405/MC5410, made in Rostov-on-Don, Russia) and vt100-compatible programmable colr display. Some models were equipped by 5MB RD50-like HDD (sometime these HDDs worked ;). No direct DEC analogue. - DWK-5 is based on the 1801BM4, with the same peripherals as the DWK-4. No one has yet admitted to having seen one, though. - * Elektronika-85, models MC0585 and MC0585.1. Used the 1811B1 processor, and had 512KB of memory (on the motherboard, rather than the DEC Pro's CTI-slot memory). There were three hard disk options: 5MB MC5401 (made in Rostov-on-Don), 10MB MC5402 (Rostov-on-Don) and CM5508 (Bulgaria), and 20MB MC5405 and MC5410 (Rostov-on-Don). The system is still in production in Voronezh, Russia, not far from Rostov-on-Don. There's a rumour that some later E-85s were produced with the 1831BM1 processor, but no one admits to having seen them. - * TPA-11/170. From Hungary. A J11-based microPDP-clone, designed around 1986-1987. - * TPA-EMU-11. A microprogrammable universal processor built on a UBUS board. It could be reprogrammed, but the basic microcode made it behave like a -11. I don't know if this beast was ever used, or if it was only planned. - * MICRO 11/23 SYSTEM 2500 TEAM COMPUTER. Produced by MIKI, did several (metric) QBUS systems based on Elektronika's CPU products (the M2 and M6, LSI-11 and KDF-11A clones, respectively). The PSU, CPU, and SLUs are Elektronika boards, everything else (parallel port, disk controllers, floppy controller, enclosure) was made by MIKI. "Kind of" OEM. - - HOME/SCHOOL COMPUTERS - * UKNC - designed to be basic School computer of Gorbachev's period of '80s. Proprietary design and peripherals. The MC0511 has two 1801WM2 CPUs. The "system" CPU has 56KB of regular memory, 8K I/O page, and 8K of hidden memory (see WM2 discussion below). The "peripheral" processor has 32KB RAM and 32KB PROM with built-in peripheral service routines. Also, this machine has a 3*32KB graphic video memory. Originally, it came with two floppies and no hard disk. Several MFM and IDE controllers have become available since then, however. - * BK-001x - first Soviet home PC, based on 11/2 CPU with proprietary chipset to serve RAM/Peripherals. 32Kb RAM, no OS - ROM BASIC or FOCAL interpreters. In the SU this computer had a success similar to TRS-80. Late models had more memory and CPU from DWK-3. Many enthusiasts created peripherals to this beast as it has QBus-compatible socket on the rear side. Note that it shipped with no operating system because it shipped with no peripherals. Hence the provisioning of such by enthusiasts. Several OS options now exist: many variants of RT-11, ANDOS (http://www.df.ru/~andos/), MKDOS, CSIDOS, et cetera. - PROPRIETARY BUS - TPA-11/440. From Hungary. 32-bit internal bus called the X-bus, but since there weren't many devices for it (only the ones the KFKI (where the TPA's were built) produced), it used the UBUS (KFKI-version of the UNIBUS, electronically the same with mechanical differences). Its designers said it had 0.7-0.8 of the performance of the MicroVAX II (which was introduced by Digital around the same time), but users say it was less (around 0.6-0.7). - TPA-11/420. Based on the J-11 chip, with the X-bus of the TPA-11/440. Chips There were several chip-sets made, corresponding (usually) to what DEC produced. - 581. The first chip-set was the 581 which involves many chips marked as 581. The 581IK1,IK2 is the main manager (controller, "heart") of the computer. 581RUx are memory chips which involve processor commands. - 1801. There are four models: 1801WM1, WM2, WM3, WM4. They are very different between each other, as described below. There's been some indication that the 1806 and 1836 prefixes have also been used in conjunction with the WMn numbers to mean the same basic chip. The significance of the prefix value has not yet been reported. - WM1. Exactly an 11/03 without FIS instructions. This chip is in a 42 pin planar package. Up to four processors could be connected into a single SMP system. No such system was put into production, but a two-processor proof-of-concept system was made. Apparently this was not originally intended as a PDP-11-compatible processor. For those that can read Russian, there's a discussion on this available via DejaNews starting at http://www.dejanews.com/getdoc.xp?AN=228171597. - WM2. Similar to the 11/03, complete with EIS (but no FIS) instructions. The packaging is a 40 pin ceramic DIP, and the pinout is noticeably different from the WM1. When an FIS instruction is encountered, a synchronous trap to "a hidden memory area" is taken, with vector 160XXX (exact vector not reported). When this trap is taken, the I/O page is "disconnected", and the hidden memory bank is switched in. The FPU handler is in this "hidden" memory. - WM3. No apparent DEC equivalent, although similar to the 11/70 or 11/73, but 11/70 is large, while WM3 is smaller then F-11! It has a 32-bit internal bus. It is not a J-11. - WM4. Another internally-32-bit processor. It is relatively fast, in the range of 16-25 MHz. Very limited quantities were produced due to low yields in the Soviet chip fabs (i.e., it was uneconomical to produce). All of these processors use standard controllers, special support chips are marked as 1801 series (1801WP1, etc). The base 1801WP1 chip is a clear universal programmed matrix with Q-Bus compatible interface logic. This allows one to build a number of custom ASICs using EPROM-like programming of non-permanent "matrix" logic. So you have a possibility to create single-chip device controllers based on that uniform base chip. In fact, most of 1801WP1-xxx chips are controllers or interface chips. All matrices MUST be programmed at the plants, there is NO WAY to reprogram/program them like EPROM chips. For example, some WP1 chips are: - 1801WP1-027 - Bubble Memory Controller (together with -032) - 1801WP1-030 - DRAM interface - 1801WP1-032 - Bubble Memory Controller (together with -027) - 1801WP1-033 - 8" Floppy disk controller (DX:/DY:), can also act as a parallel port controller - 1801WP1-035 - ASYNC port controller - 1801WP1-097 - 5.25" Floppy disk controller (MY:) Editor's note: I believe this is equivalent to a Programmable Gate Array (PGA), as opposed to an FPGA (Field PGA). More information is available at http://www.hitex.com/chipdir/soviet/index.htm. - 1811. A complete analogue of the F-11. It uses chips marked 1811. The 1811-series processor is marked 1811WM1, but there is no WM2, WM3, etc. All chips in this family are in 40 pin DIP packages. Some of the support chips are: - 1811WU2, WU3. Provide floating-point instructions, 46 extended instructions. - 1811WM1 is the main 11/23 processor. - 1811WU1 is the Microm containing the 92 standard instructions. - 1811WT is the memory extender to access 4096KB (22bit support). - 1831. A clone of either the J-11 or the T-11. Reports differ. - 581. The chips in the base family were all 42 pin planar packages. - 581IK1. Micro-programmed ALU. - 581IK2. Interface and maintenance chip for IK1. - 581RU1,2,3. Microms. RU1 and RU2 held the standard instruction set. RU3 had the EIS/FIS. - 581VE1. Relatively rare, this chip combined all of the above 581-family chips into a single 48 pin package. More Information More TPA-specific information may be found at http://www.telnet.hu/hamster/tpa/e_index.html. More general Warsaw Pact PDP-11 information is available at http://www.telnet.hu/hamster/pdp-11/index.html. Cyrillic and General Nomenclature Information provided by Alexey Chupahin: I've been told that the Cyrillic V is best represented as W in the Roman alphabet. Thus, you're referring to the DWK-*, right? Yes, DWK and DVK is the same name. I've gotten information on 1801BM*, 1801VM*, and 1801WM*. Are these all the same thing, or are the letters really different? I believe the WM and VM to be the same. What is BM? Yes, VM (WM) is BM in Cyrillic. Chips, exported to German or other countrieswas marked as 'BM', if I remember, so I write 'BM' instead 'VM' or 'WM'. Unfortunately, I don't know (and my friends) what is 'BM' meaning. All russian processors (DEC or Intel compatible) are marked as 'BM'. The letter 'K' before processor model(number) means 'ceramic box'. K1811BM1 for example. Can "MC" be interpreted as "machine"? As in, an MC prefix means this is a model/system designator, as opposed to being a chip designator? Hmm this is very interesting question.The first line of computers ( IBM/360 compatible ) and peripheral devices designed for it was named EC in cyrillic.(ES in English). EC means 'United Series' in Russian. DEC minicomputers PDP-11 series and peripheral devices was named 'CM'.(SM) 'CM' - 'Small Series'. CM-3, CM-4 are first models., CM1425 - one of the latest, with 2MB-4MB of memory, processor 1831BM1 (J-11 analogue). CM5508 - is 10MB hard disk, CM5509 - 30MB hard disk, CM6329 - Epson compatible matrix printer. Series 'MC' is another. Usually MC is "smaller" than 'CM'. 'MC' means personal computer equipment. MC0585 - Elektronika-85, MC0502 - DWK's. ======================================================== Part Number Format Every DEC component part has a 2-5-2 number. Sometimes it also has another designator, like an M-series module number*. In the 2-5-2 numbering system the first 2 digits denote the part class (for example, 23 - ROMS/PROMS/EPROMS, 29 - vendor parts), the middle 5 digits denote the unique part, and the last 2 digits denote a particular variation. Note that not all 2-5-2 part "numbers" are numeric - things like manuals are EK-series (EK was originally "Education Services- hardcopy"). *Note: technically, M-series parts are 00-Mnnnn-00, where the 0's don't display. An RQDX1, M8639-YA, is 00-M8639-YA, but it also has other 2-5-2 part numbers (there should be a 54-series etched PCB number, for example) Explanation provided by Terry Kennedy. ======================================================== PDP-11 Relative Performance From a chart in the 1978 "Computer Engineering" 11/03 11/04 11/05 11/20 11/34 11/34c 11/40 11/60 11/45 11/55 11/70 ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- Perf(1) 1 2.8 2.5 3.1 3.5 7.3 3.6 27 41 36 core 13 mos 23 Bipolar 41 Whets 26 18 13 20 204 262 57 592 725 671 core 260 mos 335 Bipolar 362 (1) performance is for the basic instruction set relative to the 11/03 From a chart in the 1987 "PDP-11 Systems Handbook" 11/23 11/53 11/73 11/83 11/93 ----- ----- ----- ----- ----- CPU F-11 J-11 J-11 J-11 J-11 Microcycle(ns) 300 267 267 222 222 Clock (MHz) ? 15 15 18 18 Performance 0.2 0.5 0.7 1.2 1.4 (11/70 = 1) Cache no no yes yes no Floating-Pt opt no no yes yes Coprocessor NOTE: The 11/93's memory was effectively all cache, so there was no need for a separate cache subsystem. NOTE: The 11/93 vs. 11/70 factor was taken from the "PDP-11 20th Anniversary Systems and Options Catalog Supplement", May 1990. And by merging the data from both charts, sorting by model number: 50 - P r 45 _ e e 40 - - r l 35 | - f a 30 | _ o t 25 | - e i 20 | - m v 15 _ a e 10 n 9 c t 8 e o 7 - - 6 f 1 5 a 1 4 _ _ c / 3 - _ - t 0 2 o 3 1 - r 0_________________M_o_d_e_l_s___________________ 0 0 0 2 2 3 3 4 4 5 5 6 7 7 8 9 3 4 5 0 3 4 4 0 5 3 5 0 0 3 3 3 c Sorting by introduction date gives: P r 45 _ e e 40 - - r l 35 | - f a 30 | _ o t 25 | - e i 20 | - m v 15 _ a e 10 n 9 c t 8 e o 7 - - 6 f 1 5 a 1 4 _ _ c / 3 - _ - t 0 2 o 3 1 - r 0_________________M_o_d_e_l_s________________ 2 4 4 0 7 5 0 0 3 6 3 2 7 5 8 0 5 0 5 0 5 3 4 4 0 4 3 3 3 3 c [I was tempted to label the vertical index of the chart in PUPs (PDP-11 Units of Performance), but resisted the temptation. :-) -MMcC] Also, from the table of UNIBUS-PDP-11s performances the micro-cycle timings for the machines listed there : 11/03 11/04 11/05 11/34 11/40 11/45 11/60 u-cycle 400 260 300 180/ 140/ 150 170 (ns) 340 200/ 300 Generally, earlier model PDP-11s with odd numbers are OEM machines and even-numbered ones are end-user machines. [11/15, 11/35, 11/05, (but not 11/45 or 11/55) vs. 11/20, 11/40, 11/10, 11/34, 11/44, 11/70]. This carried on in a variation to the later model numbers where the odd numbers became Q-Bus machines aimed at OEMs and the even-numbered were UNIBUS machines were intended for end-users. Thus the Qbus 11/03, /23, /53, /73, and /93 are aimed at OEMs and the UNIBUS 11/04, /24, /54, /7?, and /94 are aimed at the end-user market. Most of the PDP-11 line bore the standard cyan (maroon) and magenta (purple) colors. The /55 and some of the integrated systems were blue and green, as were the DEC-10 FEP 40's and some later front-panel-less /70's. The 11/60 came in the low boy (VAX) style. The 11/34 and the later UNIBUS (/24, /44) came in the white single fronts. ======================================================== What operating systems were written for the PDP-11? CAPS-11 Cassette Based Programme development System. CTS-300 There's some confusion as to whether this is just a re-packaged version of RT-11, or a time-sharing system layered on top of RT-11. CTS-500 A repackaged RSTS. As remembered by Paul Koning, a former RSTS developer: CTS-500 is indeed repackaged RSTS. RSTS itself is a timesharing system, you don't need to layer anything on top of it. The packaging included, if I remember correctly, some stuff aimed at business applications such as an indexed file system. (This predates the support of RMS-11 in RSTS, and RMS-11 basically eliminated the reason for having CTS-500.) There were some PDP-11s with special paint jobs (blue rather than maroon) and bezels, and also I think lower cabinets, as part of the CTS-500 effort. DOS/BATCH Duress Written for the PDP-11/45 in 1972-1973 mainly by Russ Atkinson, Roger Haskin and Perry Emrath, all of University of Illinois Urbana, for a Chicago company named Datalogics (which was consumed by Frame, and subsequently by Adobe). Duress was similar to Dec's DOS to the outside user. The motivation for writing the system was to take full advantage of the addressing modes of the 11/45, and may indeed be the only working system to use all three addressing modes. The system used K-space for the low- level kernel, device drivers and task management; S-space (Supervisor) for the disk file system; and U (user) for application code. Almost all other systems ignored S-space and put the entire OS in K-space. This implementation effectively doubled the amount of resident memory available for the OS. The system was used for a phototypesetting system for the State of Wisconsin Legislature, and later was used for a variety of financial and newspaper typesetting and editing systems. FUZZBALL University of Delaware, David L Mills. Used for TCP/IP, NTP, Packet Radio, Hello Routing protocol research, complete with FAX facility, boots from an RT11 system, uses DEQNA UNIBUS, PROTEON Unibus ethernet cards. Some still hiding away. GAMMA-11. RT-11-derived operating system for Nuclear Medicine, supporting VT11 and VSV11 displays, with image analysis software and ultimately sold by DEC around 1985/6 to Philips Medical Systems. HT-11 Heathkit's hacked version of RT-11, wouldn't run on a "real" PDP-11. IAS Interactive Application System. Multi-purpose multiprogramming system. This was a derivative of RSX11-D, with additional features to make it more of a time-sharing system. It also was specifically aimed at the 11/70, while RSX11-D was for the 18-bit machines like the 11/45. There is some suspicion that the intention was to make RSTS go away, but RSTS started supporting more languages than just BASIC and ended up outliving IAS. MERTS (MERTSS?) A virtual operating system that could run Unix as a process. Several machines at BTL ran MERTS. Micropower Pascal Not just a compiler, but a complete RT kernel product that could also be (and often was) programmed in assembly language as well. Folks who never used it were often confused by the unfortunate choice of name. Many large corporations used it, eventually migrating to VAXELN, which was similar in many respects. By V2.5, MPP was highly reliable. The customized Pascal compiler had some issues, but I did most of my development in MACRO-11. We built ROM-based high-speed trunked radio system controllers with it at GE, and found it very satisfactory. MTS The Multi-Tasking System written in RTL/2 by SPL. It was used for most projects in the 1970s until RSX-11M with RTL/2 became reliable and easier to use (Philip Hull). MUMPS-11 Massachusetts General Hospital Multi-User Multi-Processing System. A language, an operating system and a DBMS all in one. PC11 (Decus 11-501). Process Control Operating System, developed originally by Pilkington UK for Glass applications, extended by various users and licencees. Used by ACI Glass in Australia, with DEC IP11 industrial I/O, on five or six sites. Have DECUS Disks, plus repaired stuff from John Gaunt ex ACI Australia. From Ken Kirkby. RSTS, RSTS/E Resource Sharing/Time Sharing. General purpose time-sharing system. RT-11 Real Time. Foreground/Background or Single Job operating system. RSX-11 Resource Sharing eXecutive. Multiprogramming system. RSX-11B/C, Micro/RSX RSX-11/D Large real-time multiprogramming system. RSX-11/M Small to moderate-sized real-time multiprogramming system. RSX-11/M+ Extended RSX-11/M. RSX-11/S Execute-only real-time multiprogramming system. RSX-20F Modified version of RXS-11M that ran in the PDP-11/40 that was the console front-end for the PDP-10 Model KL. Primary console terminal for KL, KLINIK dial-up maintenance console, async terminals (hardwire and dial-up), line printer, card reader. Used part of the PDP-10's RP06 as its file system. The PDP-11 was used to start, stop, and load microcode into the PDP-10. Softech Microsystems UCSD(TM) System with UCSD Pascal. Sphere, from Infosphere - Portland Oregon 1981-87. Developed on PDP11/23's by Evan Solley, and Rick Braithwaite, ran on KXT11A-AB' Falcons, complete with RLO2/RlO1, TU58, and RX02 drivers - used for embedded systems. Stoic-like syntax. Multi-tasking, built-in editor, ... TRAX Transaction Processing system. TRIPOS TRIPOS - A Portable Operating System for Mini-Computers, Software Practice and Experience, Volume 9, pp 513-526 (1979) by M. Richards, A. R. Aylward, P. Bond, R. D. Evans and B. J. Knight. The web page for TRIPOS is at http://www.cl.cam.ac.uk/users/mr/Tripos.html, but it does not mention the PDP-11 support. TRIPOS is written mostly in BCPL. TSX-11 Multi-user enhancements to RT-11 (third-party). Ultrix Digital's implementation/port of BSD UNIX. Unix (tm) Much/most of Unix was developed on PDP-11s. The source code for PDP-11-relevant versions of Unix is owned by the Santa Cruz Operation. They have been offering a low-cost "Ancient Unix License" for a while now, and as of April 18, 2000, dropped the licensing fee completely. Some relevant web links are: The SCO no-license-fee press release: http://www.sco.com/press/releases/2000/6927.html The PDP Unix Preservation Society's home page: http://minnie.cs.adfa.edu.au/PUPS/ Marshall Kirk McKusick's CSRG Archive CD-ROM of all the BSD releases: http://www.mckusick.com/csrg/index.html Venix A third-party implementation/port of UNIX. ======================================================== What programming languages are supported on the PDP-11? - Assembler - Algol-60. Apparently originally started on the PDP-8 and brought to the PDP-11. Inspired by the Burroughs 6000 series (mainframe) extended Algol, and in fact you can think of it as a combination compiler for a Burroughs-like imaginary machine combined with an emulator for that machine on the PDP11. (Sort of like the Java virtual machine, ah, how things come back around...) (from Paul Koning) - Algol-68. CMU did a port of an Algol-68 implementation. I have the DECtapes (!) for half of it, but unfortunately only half or I would have brought it up. If someone can get me the whole thing I'd be interested... (Paul Koning) - APL - BASIC, BASIC-plus2 - BCPL - Bliss-11 (or BLISS-16?) Both names exist, actually, and they refer to different things. One is from CMU, the original home of Bliss. I think that one ran on a 10 and crosscompiled for the 11, but I'm not sure of that. The other is a crosscompiler from VAX to 11. And I don't remember which name refers to which one. Paul Koning - C - Cobol - Coral-11, also known as Coral-66. A British real-time language, with roots from ICI. A DEC Pricebook product running under RSX. I can't seem to locate the product code, but any running RSX system shows references to CORAL in its source. Definitely used in the UK and Australia. Something of a predecessor to Ada, in that it was a language intended for military programming jobs. ken @&nbps;terrigal.net.au and Paul Koning - DIBOL - Focal - FORTH. Originally done by a group in California; Paul Koning extended it for RSTS and used it to build several tools, among which an interactive system crash dump analyzer similar to the VMS tool "SDA" (and also called SDA). It shipped as unsupported software with RSTS 10.1. A version was also available from Forth, Inc. - Fortran IV, Fortran IV+, Fortran 77 - KOALA. An obscure language [that] I don't remember if [it] ever made it outside DEC. It was created for one of those grandiose failures that Ken Olsen became so notorious for. Started as the next great new implementation language, it ended up being merely the language that WPS-PLUS was written in, both for VMS and PDP11s. That provided an early example of "the virtual disease" -- showing that you *cannot* port a large application from a 32-bit machine to a 16-bit one. (Paul Koning) - LIL (?) - LisP - MUMPS - Macro - Micropower Pascal. A Pascal variant that came as part of the Micropower Pascal real-time OS. See faq.pages/pdpOSes.html. - Modula-2 - Pascal - Prolog - RTL. Developed initially from work done by Britain's Imperial Chemical Industries (ICI), a Dow equivalent. Granted British Standard language status, and a European standard. Main data object is a BRICK. Good structured programs result. Never used in Australia, AFAIK, but quoted several times. Used extensively in South Africa, on industrial control systems such as ELCON from E.L. Bateman, Sth Africa. I have source, RTL compilers and manuals from those systems, running on RSX11M+ V3.0. Ported by SPL to other platforms. I did get some prices a couple of years back for the 68K platform. From Ken Kirkby. Philip Hull reports that there was an operating system written in RTL/2 called MTS. - RTL/2. This language was developed by a company called SPL (which stood for Systems Programming Limited International) in the United Kingdom. (I have the books on it somewhere). It's a language very similar to C, almost a combination of C and Pascal but leaning more to C. The language is very easy to use. Its compiler compiles the code into Macro-11 source and from there you compile it with MAC and build the task with TKB. The major feature is the ability to drop into code (Macro-11 assembler) just like in C by using a statement - CODE - from then on you can write in Macro-11 - you can return to RTL/2 by using the statement *RTL; . You just have to ensure that you return the stack to the appropriate state before you go back to RTL/2 but that's not difficult when you are used to it. This gives you enormous benefits as you can use the entire set of MACROS supplied by DEC as well as write your code in a higher level langauge. A major benefit over FORTRAN and other higher level languages that were written for the PDP where you are restricted to the functions provided in the language. RTL/2 comes with large function libraries of its own. I know that this language is still in use in Europe and South Africa and possibly in Aussie as well - PDP's haven't died out in the above countries yet - I dont know how many are still in use in the USA. If you would like any other information or examples of the langauge feel free to contact me. From Wayne Devereux. - Softech Microsystems UCSD(TM) System with UCSD Pascal. ======================================================== Hobbyist licenses for PDP-11 operating systems At this time [Mon, 20 Dec 1999], hobbyist licenses are not available for the PDP-11 operating systems and other software available from Mentec and sold by Compaq. Ownership of IAS, POS, Ultrix-11 and MUMPS does not rest with Mentec and therefore the status of hobbyist licences may differ for these products. Permission to run old PDP-11 software versions on the Supnik emulator does exist, but this does not apply to other platforms or emulators. Check the restrictions with the emulator. All PDP-11 software is still subject to requiring a valid licence, whether you want to run version 1 or the latest. Be careful when copying or selling software that you do not accidentally violate the licence. I should add that Mentec *are* listening and work has been and is continuing to be done on this score. Alas, it is not as simple as Mentec saying "We are going to issue Hobbyist licenses" ... were that the case, then it would have been done long ago. Existing PDP-11 Software Licenses > have no experience dealing with DEC software or software licenses, and > frankly, all this licensing gobbledy-gook makes my head spin.... Believe me that even those of us who have been involved with Digital licensing for more than 20 years can still go into headspins with its complexities! When you buy licensed software, there are two parts ... the first is the license itself ... the license gives you permission to use the software on media that you purchase according to the terms of the license, which usually includes terms like don't copy, don't use on unlicensed machines and so on. The second thing you purchase is the media with the software on it ... and this usually includes the cost of the media itself and development and production costs. In the case of Digital PDP-11 software, you can sell licensed software if you also transfer the license, which is where your wanting to sell the software may come unglued. Or if the purchaser is willing to purchase a new license. I know it seems kind of crazy to have to purchase a new license for old versions of software, but that's the way it is, since the license and media are sold separately. Upgrading versions also throws licensing issues into a headspin, in part because of inconsistencies in earlier Digital policies in this area. Basically for a license to be transferrable to new versions, you must have been on a maintenance contract, otherwise you must purchase a new license or an upgrade license. Upgrade licenses are available under limited circumstances. Provided by Stuart Brook of Mentec ======================================================== Memory address convention (for this FAQ), and the GPRs There is a certain amount of confusion about memory addressing representation due to the fact that the PDP-11 was originally launched with 16-bit addressing, but was extended through 18-bit to 22-bit over time. On the 11/20, the processor status word (PSW), the topmost addressable location, would have address 177776, while on the 11/40 the address would be 777776, and on the 11/70, 17777776. Of course the hardware also helped in bit extending for you if you toggled in 177776 in an 11/70.... For the purposes of this FAQ I propose to take the middle ground and refer to addresses as if we were talking about an 11/40. Make your mental adjustments as appropriate. There is one further area of confusion. Addresses are byte aligned, with an even address referring to a word (unless this is a byte operation in which case the lower byte of the word is the target) and an odd address specifying the upper byte of the word. In English, memory locations are incremented up in steps of 2. There is, of course, an exception. The General Purpose Registers (GPRs) had addresses that incremented in steps of 1. R0 is 777700, R1 is 777701 .. R6(Kernel) is 777706, R7(Kernel) is 777707. Later models had a second set of GPRs at 777710 through 777717. The complication does not stop here, though. The Kernel Stack pointer (SP) is at 777706, the supervisor SP at 777716 and the User SP is at 777717. It should be noted that using memory addresses to get at the registers is not supported by the LSI-11 chip sets. This applies to the PSW as well as the GPRs. For the former register, the LSI-11 introduced MTPS and MFPS (move to/from processor status). Obviously, there was no need for extra instructions for getting at the GPRs.... ======================================================== What is the PDP-11 instruction set? The instruction set of the PDP-11 was designed towards a clean, general, symmetric instruction set. It can be used as a register-based, stack-based, or memory-based machine, depending on the programmer's preferences. Interrupt responsiveness is also important, supported with multiple interrupt levels for real-time computing as well as allowing for a separate interrupt handler for each device that generates interrupts. Word length is 16 bits with the leftmost, most significant bit (MSB) being bit 15. There are eight general registers of 16 bits each. Register 7 is the program counter (PC) and, by convention, Register 6 is the stack pointer (SP). There is also a Processor Status Register/Word (PSW) which indicates the 4 condition code bits (N, Z, V, C), the Trace Trap bit, processor interrupt priority, and 4 bits for current and previous operating modes. Addressing on the -11 is linear from memory address 0 through 177777. Memory management allows access to physical memory with addresses of up to 22 bits (17777777). All I/O devices, registers etc are addressed as if they were part of memory. These live in the 4KW of reserved memory space at the top of the addressing range. Additionally, on most implementations of the PDP-11 architecture, the processor's registers are memory-mapped to the range 17777700-17777717 (there are many control registers beyond just the general registers, the specifics vary between implementations). Thus Register 2 (R2) has an address of 17777702. All word memory addresses are even, except for registers. In byte operations, an even address specifies the least-significant byte and an odd address specifies the most-significant byte. Specifying an odd byte in a word operation will return an odd address trap. Memory addresses from 0 to 400 octal are reserved for various exception traps such as timeouts, reserved instructions, parity, etc., and device interrupts. Addressing for the Single Operand, Double Operand and Jump instructions is achieved via six bits: _ _ _ _ _ _ |x|x|x|_|_|_| |Mode |Reg | where the modes are as follows: (Reg = Register, Def = Deferred) Mode 0 Reg Direct addressing of the register Mode 1 Reg Def Contents of Reg is the address Mode 2 AutoIncr Contents of Reg is the address, then Reg incremented Mode 3 AutoIncrDef Content of Reg is addr of addr, then Reg Incremented Mode 4 AutoDecr Reg is decremented then contents is address Mode 5 AutoDecrDef Reg is decremented then contents is addr of addr Mode 6 Index Contents of Reg + Following word is address Mode 7 IndexDef Contents of Reg + Following word is addr of addr Note that the right-most bit of the mode is an indirection bit. Although not special cases, when dealing with R7 (aka the PC), some of these operations are called different things: _ _ _ _ _ _ |x|x|x|1|1|1| |Mode | R7 | Mode 2 Immediate Operand follows the instruction Mode 3 Absolute Address of Operand follows the instruction Mode 6 Relative Instr address+4+Next word is Address Mode 7 RelativeDef Instr address+4+Next word is Address of address Mainstream instructions are broken into Single operand and Double operand instructions, which in turn can be word or byte instructions. Double Operand Instructions _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ |b|i|i|i|s|s|s|s|s|s|d|d|d|d|d|d| | | | : | : | | | Op | Source | Dest | Bit 15, b, generally selects between word-sized (b=0) and byte-sized (b=1) operands. In the table below, the mnemonics and names are given in the order b=0/b=1. The double operand instructions are: b 000 ssssss dddddd Non-double-operand instructions. b 001 ssssss dddddd -- MOV/MOVB Move Word/Byte Moves a value from source to destination. b 010 ssssss dddddd -- CMP/CMPB Compare Word/Byte Compares values by subtracting the destination from the source, setting the condition codes, and then discarding the result of the subtraction. b 011 ssssss dddddd -- BIT/BITB Bit Test Word/Byte Performs a bit-wise AND of the source and the destination, sets the condition codes, and then discards the result of the AND. b 100 ssssss dddddd -- BIC/BICB Bit Clear Word/Byte For each bit set in the source, that bit is cleared in the destination. This is accomplished by taking the ones-complement of the source and ANDing it with the destination. The result of the AND is stored in the destination. b 101 ssssss dddddd -- BIS/BISB Bit Set Word/Byte For each bit set in the source, that bit is set in the destination. This is accomplished by ORing the source and destination, and storing the result in the destination. b 110 ssssss dddddd -- ADD/SUB Add/Subtract Word Adds the source and destination, storing the results in the destination. Subtracts the source from the destination, storing the results in the destination. Note that this is a special case for b=1, in that it does not indicate that byte-wide operands are used. b 111 xxxxxx xxxxxx Arithmetic functions not supported by all implementations of the PDP-11 architecture. Single Operand Instructions _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ |b|0|0|0|i|i|i|i|i|i|d|d|d|d|d|d| | | | : | : | | | |Instruction| Dest | Bit 15, b, generally selects between word-sized (b=0) and byte-sized (b=1) operands. In the table below, the mnemonics and names are given in the order b=0/b=1. Unless otherwise stated, the operand is read for the data to operate on, and the result is then written over that data. The single operand instructions are: b 000 000 011 dddddd -- SWAB/BPL Swap Bytes/Branch Plus Swap bytes exchanges the two bytes found in the destination, writing the result back to it. The branch (b=1) is described in the section on branches, below. Note that SWAB is actually a bit pattern from the range reserved for branches. This particular pattern is otherwise unused, as it would be a modification of BR, Branch Always, which has no obvious semantics. b 000 101 000 dddddd -- CLR/CLRB Clear Word/Byte Sets all the bits in destination to zero. b 000 101 001 dddddd -- COM/COMB Complement Word/Byte Calculates the ones-complement of the operand, and stores it. The ones-complement is formed by inverting each bit (0->1, 1->0) independently. b 000 010 010 dddddd -- INC/INCB Increment Word/Byte Adds one to the destination. b 000 101 011 dddddd -- DEC/DECB Decrement Word/Byte Subtracts one from the destination. b 000 101 100 dddddd -- NEG/NEGB Negate Word/Byte Calculates the twos-complement of the operand, and stores it. The twos-complement is formed by adding one to the ones-complement. The effect is the same as subtracting the operand from zero. b 000 101 101 dddddd -- ADC/ADCB Add Carry Word/Byte Adds the current value of the carry flag to the destination. This is useful for implementing arithmetic subroutines with more than word-sized operands. b 000 101 110 dddddd -- SBC/SBCB Subtract Carry Word/Byte Subtracts the current value of the carry flag from the destination. This is useful for implementing arithmetic subroutines with more than word-sized operands. b 000 101 111 dddddd -- TST/TSTB Test Word/Byte Sets the N (negative) and Z (zero) condition codes based on the value of the operand. b 000 110 000 dddddd -- ROR/RORB Rotate Right Word/Byte Rotates the bits of the operand one position to the right. The right-most bit is placed in the carry flag, and the carry flag is copied to the left-most bit (bit 15) of the operand. b 000 110 001 dddddd -- ROL/ROLB Rotate Left Word/Byte Rotates the bits of the operand one position to the left. The left-most bit is placed in the carry flag, and the carry flag is copied to the right-most bit (bit 0) of the operand. b 000 110 010 dddddd -- ASR/ASRB Arithmetic Shift Right Word/Byte Shifts the bits of the operand one position to the right. The left-most bit is duplicated. The effect is to perform a signed division by 2. b 000 110 011 dddddd -- ASL/ASLB Arithmetic Shift Left Word/Byte Shifts the bits of the operand one position to the left. The right-most bit is set to zero. The effect is to perform a signed multiplication by 2. b 000 110 100 dddddd -- MARK/MTPS Mark/Move To Processor Status Mark is used as part of one of the subroutine call/ return sequences. The operand is the number of parameters. MTPS is only on LSI-11s, and is used to move a byte to the processor status word. This is needed because the LSI-11 does not support accessing registers via memory addresses. b 000 110 101 dddddd -- MFPI/MFPD Move From Prev. Instruction/Data Pushes a word onto the current R6 stack from the operand address in the previous address space, as indicated in the PSW. On PDP-11s that do not support separate instruction and data spaces, MFPD is treated the same as MFPI. b 000 110 110 dddddd -- MTPI/MTPD Move To Previous Instruction/Data Pops a word from the current stack as indicated in the PSW to the operand address in the previous address space, as indicated in the PSW. On PDP-11s that do not support separate instruction and data spaces, MTPD is treated the same as MTPI. b 000 110 111 dddddd -- SXT/MFPS Sign Extend/Move From Processor Status SXT sets the destination to zero if the N (negative) flag is clear, or to all ones if N is set. This is useful for implementing arithmetic subroutines with more than word-sized operands. MFPS copies the processor status byte to the indicated register. This only exists on LSI-11s, and is needed there because those systems don't support accessing registers via memory addresses. Branches _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ |b|0|0|0|b|b|b|b|d|d|d|d|d|d|d|d| | Branch Code | Destination | The destination of a branch is +127 to -128 words from the word following the branch instruction itself. This seems slightly odd, until you realize the sequence of events: the branch instruction is read from memory and the PC incremented. If the branch is to be taken, the offset is then added to the current value of the PC. Since the PC has already been incremented, the offset is thus relative to the following word. Note that all branch instructions are one word long. The various branches test the values of specific condition codes, and if the tests succeed, the branch is taken. The condition codes are N (negative), Z (zero), C (carry), and V (overflow). In the table below, the branch tests are shown as boolean expressions. `x' stands for exclusive-OR. `v' stands for inclusive-OR. 0 000 000 1dd dddddd BR: Branch Always 0 000 001 0dd dddddd BNE: Branch if Not Equal (Z==0) 0 000 001 1dd dddddd BEQ: Branch if EQual (Z==1) 0 000 010 0dd dddddd BGE: Branch if Greater or Equal (NxV == 0) 0 000 010 1dd dddddd BLT: Branch if Less Than (NxV == 1) 0 000 011 0dd dddddd BGT: Branch if Greater Than (Zv(NxV) == 0) 0 000 011 1dd dddddd BLE: Branch if Less or Equal (Zv(NxV) == 1) 1 000 000 0dd dddddd BPL: Branch if PLus (N == 0) 1 000 000 1dd dddddd BMI: Branch if MInus (N == 1) 1 000 001 0dd dddddd BHI: Branch if HIgher (C==0 and Z==0) 1 000 001 1dd dddddd BLOS: Branch if Lower Or Same (CvZ == 1) 1 000 010 0dd dddddd BVC: Branch if oVerflow Clear (V == 0) 1 000 010 1dd dddddd BVS: Branch if oVerflow set (V == 1) 1 000 011 0dd dddddd BCC: Branch if Carry Clear (C == 0) also known as BHIS: Branch if Higher Or Same 1 000 011 1dd dddddd BCS: Branch if Carry Set (C == 1) also known as BLO: Branch if Lower Condition Code Operations _ _ _ _ _ _ _ _ _ _:_ _ _:_ _ _ |0|0|0|0|0|0|0|0|1|0|1|s|N|Z|V|C| | O p c o d e | | Mask | General opcode 000240x. Set/Clear corresponding bits depending on sense of bit 04 (set=1, clear=0). Codes 240 and 260 set/clear no bits and are, thus, used as NOP. Although specific mnemonic are provided for each flag and all flags, any combination may actually be set or cleared at a time. General mnemonics are: CLx Clear x, where x is N, Z, V, or C SEx Set x, where x is N, Z, V, or C CCC Clear all condition codes SCC Set all condition codes 0 000 000 010 1s0 000 NOP/NOP: No Operation 0 000 000 010 1s0 001 SEC/CLC: Set/Clear Carry 0 000 000 010 1s0 010 SEV/CLV: Set/Clear Overflow 0 000 000 010 1s0 100 SEZ/CLZ: Set/Clear Zero 0 000 000 010 1s1 000 SEN/CLN: Set/Clear Negative 0 000 000 010 1s1 111 SCC/CCC: Set/Clear All Condition Codes Other, Miscellaneous _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ |0|0|0|0|1|0|0|s|s|s|d|d|d|d|d|d| | Opcode |Stack|Destination| 0 000 100 sss dddddd -- JSR Jump to Subroutine The actual sequence of steps taken is: MOV ,-(R6) MOV PC, JMP Thus, it loads the calling address into the specified source register (after saving the original contents). It then jumps to the destination. The fun part is (as usual with the PDP-11) that the PC is a general register, and the description above is the result when the PC is used as the source. _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ |0|0|0|0|0|0|0|0|1|0|0|0|0|s|s|s| | Opcode |Stack| 0 000 000 010 000 sss -- RTS ReTurn from Subroutine Undoes the effects of a JSR. For predictable results, it is suggested that the same register should be used as was named in the corresponding JSR instruction. The actual operations involved are: MOV ,PC MOV (R6)+, This is the reverse of JSR. Obviously, the finesse here too is that you can use the PC, to get what people normally consider a CALL/RETURN function. Why is it done like this then? Well, consider this example: ... JSR R0,FOO .WORD A .WORD B MOV R1,C ... FOO: MOV @(R0)+,R1 ADD @(R0)+,R1 RTS R0 This type of parameter passing is used extensively in the PDP-8 and PDP-10), for example. Also, the FORTRAN runtime system on the PDP-11 do it this way. (It is fairly easy to write a compiler who generates such a calling sequence, and then have a library of functions which expect this calling convention.) _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ |0|0|0|0|0|0|0|0|0|1|d|d|d|d|d|d| | Opcode |Destination| 0 000 000 001 ddd ddd -- JMP JuMP Loads the destination address into the PC, thus effecting an unconditional jump. Note that a trap will occur on some systems if an odd address is specified. On others, the destination is silently rounded down to the next-lower even address (i.e., the right-most bit is ignored). _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ |0|0|0|0|0|0|0|0|0|0|0|0|0|i|i|i| | | | | | | Op | 0 000 000 000 000 000 -- HALT Halts the machine Ceases I/O, and gives control to the console. Operator intervention is required to continue or restart the system. 0 000 000 000 000 001 -- WAIT WAIT for interrupt 0 000 000 000 000 010 -- RTI ReTurn from Interrupt 0 000 000 000 000 100 -- BPT BreakPoint Trap 0 000 000 000 000 101 -- RESET Initializes the system The following opcode ranges are all unused (using three bits per digit): 00 00 07 .. 00 00 77 00 02 10 .. 00 02 27 00 70 00 .. 00 77 77 07 50 40 .. 07 67 77 10 64 00 .. 10 64 77 10 67 00 .. 10 77 77 Other arithmetic and floating point instructions were added to the basic set over the years, but those listed above form the core PDP-11 instruction set. There is a comparison of PDP-11 and 80x86 floating point formats available at: ftp://ftp.dbit.com/pub/pdp11/info/fpp.txt ======================================================== Parity Back in some part of the olden days (quoting from an original 11/45 Small Computer Handbook), there was a memory parity register for each 8KW of memory. These registers had the following addresses: 772110 memory 0-8K 772112 memory 8-16K . . . 772144 memory 112-120K 772146 memory 120-124K These registers had the following bit definitions: Parity Error Type of parity controls high 4K, low 4K =1 odd parity, =0 even Halt Enable =1, halt on parity error, =0 trap to 4 Parity Disable =1, no action on parity error Initial state on power-up =0, =1 This is vintage 11/45, when the parity registers were part of the CPU. Later Unibus 11's had parity registers as part of the memory units, one register for each core block, 8KW or 16KW or 32KW. As I recall, operating systems and diagnostic software expected the parity register addresses to be jumpered for consecutive I/O page words regardless of the original intended assignments. Explanation provided by Carl Lowenstein An alternative view by Dmitry Pryanishnikov: Hm... This info seems to be incompatible with the current software. Look at HWDDF$ in RSX-11M/PLUS EXEMC.MLB: MPAR=172100. So we have up to 16 registers at addresses 172100-172136 (for example, built-in 256k memory in CM2420 has CSR @ 172100 while external memory CM3508.31 (up to 4Mb) has CSR @ 172136). Then look at [11,10]PARTY.MAC: those registers must not have consecutive I/O page addresses, RSX builds array of it's addresses during boot, so every array element points either to I/O page for existent CSR or to dummy word in memory for non-existent (there is also a bitmask of present CSRs for error logging purposes). Looking at PARTY code one can see that only bit 0 defined in those registers, and setting it will enable parity error notification (so RSX writes #1 to each one). Other bits may differ on different memory modules. During memory parity/uncorrectable ECC error memory module asserts BUS PB L UNIBUS signal thus causing current instruction abort thru vector 114(8). If it was in kernel mode, RSX prints ***EXEC PARITY ERROR STOP*** and halts. Otherwise it aborts current task and logs contents of parity registers for Error Logging. ======================================================== How Do I Set The Jumpers On... People often ask for the jumper settings or system configuration requirements for a particular PDP-11 board. Given the thousands of such boards available (from DEC as well as third-party vendors), it's impractical to include such information in this FAQ. However, Tim Shoppa has collected quite a bit, and made it available off of a link from his http://metalab.unc.edu/pub/academic/computer-science/history/pdp-11/ page. There are also many DEC Micronotes archived there. Regarding the Micronotes: The one claiming to explain the differences between the 11/70, 11/83, and 11/93 actually discusses the differences in the cache design between the 11/83 and 11/93. Will Kranz is also making various hardware-specific information available at http://www.conknet.com/~w_kranz/pdp11/pdp11.htm. ======================================================== The PDP-11 Maintenance Panel and Front Panel The PDP-11 Maintenance Panel was introduced with the 11/20. It comprised of two single height boards, a lamp driver and a lamp/switch board. Through the use of the four switches, the processor clock could be interrupted and single stepped through the ISR and BSR timing states of the 11/20. Timing state numbers, Condition Codes and certain other flags were displayed on the maintenance panels 16(?) lamps. Of course, having the machine frozen in suspended animation also facilitated the troubleshooting of the internal circuits by oscilloscope. On the 11/40 there were two slots into which a maintenance panel could be plugged. In the first slot you could single step the processor clock and cycle through the microcode program. The processor could be made to stop at a specific microcode address (MPC) set in the front panel switches. The panel could be plugged into a different slot and perform the same function for the Floating Point Processor. If you thought that the PDP-11 had wide and complex micro-instructions, you should have seen the FPP! The panel also performed the same function on the 11/05 (no floating point) and was also used on the 11/70. A good technician would have been able to determine a fault on an 11/40 and 11/70 using nothing more than the maintenance panel, front panel, and knowledge of the inter-relationships of the processor's data paths. [I am unclear whether the Maint Panel was used in later PDP-11s. I seem to remember that certain of the micro-stepping and micro-trapping functions were incorporated into the calculator-style front panels of the 11/04, /34, /44 and /60. And I draw a total blank re: the later Micro-PDP-11's. Perhaps someone can fill in some detail here? -MMcC] The front panel on the PDP-11 went through some major revisions. The original 11/20, 11/15, and later the 11/05 and 11/10, 11/40 and 11/35, 11/45, 11/50, 11/55, 11/70 and 11/74 were equipped with what the purists regard as the "real" front panels. Subsequent machines (mostly the LSI-11s) had either chicklet-calculator octal panels, or just a trio of switches of various purposes (always including Enable/ Halt). These latter had Console ODT, instead. The 11/20 panel is laid out roughly as (not to scale): +-------------------------------------------------------+ | ADDRESS REGISTER RUN BUS FETCH EXEC | | +---+---+---+---+---+---+ +---+---+ +-----+----+ | | |ooo|ooo|ooo|ooo|ooo|ooo| | o | o | | o | o | | | +---+---+---+---+---+---+ +---+---+ +-----+----+ | | DATA SRC DST ADDR | | +-+---+---+---+---+---+ +---+---+ +----+ | | |o|ooo|ooo|ooo|ooo|ooo| |ooo|ooo| | ooo| | | +-+---+---+---+---+---+ +---+---+ +----+ | | SWITCH REGISTER L E C H S T D | |\|/ +---+---+---+---+---+---+ +-+-+-+-+-+-+ +-+ | | O |ttt|ttt|ttt|ttt|ttt|ttt| |m|m|m|t|t|m| |m| | | +---+---+---+---+---+---+ +-+-+-+-+-+-+ +-+ | +-------------------------------------------------------+ The small circles are incandescent lamps (i.e., prone to burning out). The odd thing at the lower-left is the keyswitch. The 10 o'clock position is OFF, straight up is POWER, and 2 o'clock is PANEL LOCK. The lower-case `t's are toggle switches. The lower-case `m's are momentary-contact switches. They are all large paddles, coloured alternately magenta and orange. The left bank of switches are used to set the address and data registers. The action switches on the right are: - L LOAD ADDR, copies the switch register to the address register - E EXAM, loads the data register from the memory location indicated in the address register - C CONT, continues the processor from a HALT - H ENABLE/HALT, enables the processor to run if up, stops it if down - S S-INST/S-CYCLE, selects the style of single-stepping - T START, resets the system and starts the processor - D DEP, deposits the contents of the switch register in the memory location indicated by the address register. This switch must be pushed up to operate, unlike any of the others. The way ENABLE/HALT, CONT, and START work are (this is true of an 11/70 as well, and presumably of everything above an 11/40): - ENABLE/HALT: If in the HALT position the machine will HALT at the proper moment, depending on the S-INST/S-CYCLE. If in the ENABLE position, the S-INST/S-CYCLE is ignored. The 11/40 also halts the bus arbitrator, which has the side-effect of killing off any in-progress DMA transfers. The 11/45 and 11/70 do the right thing, other models have not been reported on as yet. - CONT will just start the processor at where the PC points. - START will issue a bus reset before starting. If you want to do a bus reset without running the machine, you switch to HALT, and depress START. I don't think it executes anything at that time, which would imply that START can do less than CONT, which will single-step in this case. The 11/05 economized on the front panel. LEDs replaced lamps and there was only a single row of them. They were multiplexed, and whether they displayed data or address depended on the function being performed. Action switches remained similar to the 11/20 with the possible omission of the single step. [Help needed here ...]. The switches were small and made of white plastic. The other machines mentioned above had serious front panels. Great big triangular wedge shaped keys; two rows of data and address lines; and function lights. The 11/40 had: Run, Bus, User, Processor, Console, Virtual The 11/45 and 11/55 had: User I Super I Kernel I Prog Phy User D Super D Kernel D Cons Phy Data Paths u-Address FPP/CPU BUS Register Display Register ...and a pair of rotary switches to select between the two sets of displays! The 11/70 display was similar if slightly different in detail. Of course it had 22 of those nice big Data/Address switches! With the advent of the 11/04, 11/34, and 11/60, two consoles were offered. One could go the minimalist approach and purchase the cheapie and get a Boot and Halt switch along with a Run lamp. Not exactly loved by those that needed to interact with the machines intimately! Alternatively one could purchase the more fully featured (KY11-B ?) panel with the chicklet keys and calculator face. Many technicians had their own personal chicklet panels for troubleshooting those machines ordered with the minimal panel. The 11/60 was shipped with only the calculator-style panel. I seem to recall that DEC might have relented and done likewise with later 11/34 models. More recent PDP-11s seem to have nothing more than a power switch, although I believe a button or two and a couple of LED's might lurk under the covers if you know where to look for them. ======================================================== Trivia/Humour/Stories The 11/70 Hack: The following was part of a quiz posted in a Newsgroup: 3. Tom Farrin is famous for a hack he did to DEC's PDP-11/70. This was a trace cut and jump inside the CPU which: a) increased the system clock speed by 12.5% b) enabled IEEE-compatible floating-point arithmetic c) froze the contents of the cache d) disabled the Unibus reset that occurs automatically on a bus error e) made separate instruction and data space available in user mode [....] to which Robert Herndon provided additional insight: "and the answer is listed as `E'". I was present at a lecture he gave at the 1978 Unix Users Group Conference in NYC (this was just before they asked BTL for official permission to call themselves this, and were turned down, after which the conferences became "Usenix" conferences). In it, he described how he needed the MFPI instruction (move from previous instruction space; it gets a word of data from the "previous mode"'s instruction space) in order to efficiently determine the number of arguments pushed on the stack. This was because his Lisp interpreter was too big to run without running in separate I & D spaces (type 411 binary, as opposed to 407 (unshareable), or 410 (shareable, but common address space). Running programs in separate I & D spaces was an everyday event on PDP-11s at the time, but separate I&D binaries could not use the nargs() procedure (which looked at the caller's instructions). Since his program was running in separate I & D spaces, any loads to look at the caller's instructions would simply load a word from the data space at the same address. DEC, in their wisdom, had made the MFPI and MFPD instructions privileged, so he couldn't use them to look at his instruction space. So he made a system call available to do this function, but found that it was very slow. And as he put it, that wasn't very satisfactory, and "Well, there's this NAND gate, and if you cut this wire...", and the room dissolved in laughter. And then he told us that this cut was available as a DEC field mod and gave us its number... The 407 Header If you want another bit of trivia in this vein, the 407 header number for Unix binaries is an artifact of the PDP-11's instruction set. This is a 'branch forward 7 words'. In case you installed your block-zero bootstrap without first stripping off the eight-word header, this allowed it to run anyway (since the code was position independent). Other machines have used 407 headers ever since for no good reason... [rh] 31KB in an LSI-11 John Shelton writes: In 1978 or so, I was running a Heathkit version of the LSI-11 at home, and was unsatisfied with the memory limitation of 28kb (4kb reserved for I/O space). Since I didn't have a lot of peripherals, I made sure all their I/O addresses were in the top 1k of address space, then constructed a 3kb memory card, thus having the largest memory LSI-11 around: 31kb! Fastest PDP-8 Trivia item: did you note anywhere that the 11/60 was used to implement the world's fastest PDP-8? The 8 support group for years used an 11/60 RSTS system down the hall, running custom microcode addons to implement a high speed PDP8 emulator. (Paul Koning) Rumour has it that some hacker also did this on a VAX-11/780, which would definitely out-run the 11/60 version. However, I don't believe this was used in production anywhere, and the 11/60 definitely was. Kill The Rotating Bit Games And of course, 'kill-the-rotating-bit' games on the console were a blast. These could be run from user mode, certainly under unix, and probably under the other OSes as well. The game put an initial bit in R0 and executed a wait (instruction 1). It then made a getcsw() call to the kernel to get the state of the console switch register, and XORed this result into R0. If R0 == 0, then it would flash the lights for a bit, reload R0 with a nice new value, and restart the game. Otherwise, it would rotate R0 one position and go on. (The 'wait' instruction halted the CPU until the next interrupt. Bizarrely, it was executable from user mode.) Executing from the registers In nearly all PDP11s, the GPR "addresses" work only from the console, you can't use them in a program. But they *do* work in the PDP11/05 and /10. In fact, you can put code in the GPRs. And if you do, the PC will increment by 1 rather than by 2! (It seems someone had a few spare words in the microprogram and figured this would be a useful hack. Yes indeed, it lets you test the CPU without having any working memory.) ======================================================== Who's Who? - C. Gordon Bell is generally credited with the original design of the PDP-8. He was also involved with recommending what became the PDP-11 when that design was competing with the design that probably became the NOVA, and as vice president of research, he oversaw the development of the DEC VAX family. - Alan Kotok worked with Bell in working up the original specifications of the PDP-8. - Ben Gurley designed most of the big DEC machines, starting with the PDP-1. The actual design work on the -8, however, was done by Ed deCastro, who later founded Data General to build the Nova. - Ken Olson ran DEC from the beginning. - Ed Yourdon hacked up the PAL III assembler for the -8, based on PAL II. He later became well known as a programming methodology guru. - Charles Lasner developed P?S/8, and he is widely known as the grand old man of the movement to preserve these historic machines. - Wesley Clark developed the LINC while working at Lincoln Labs; this was the first 12-bit minicomputer built with DEC parts. - Mary Allen Wilkes Clark developed the early LAP programs for the LINC. - Douglas W. Jones wrote the PDP-8 FAQ, from which the introductory "What is a PDP" is unabashedly cribbed. Most of my [MMcC] direct knowledge is of the earlier -11's and gets real hazy around the 11/5x - 11/9x boxes. However, the following contributors have helped fill in the gaps here and elsewhere in PDP-11 history, and otherwise helped with the FAQ: - Mike McCrohan - Tony Duell - Ron Natalie - Johnny Billquist - Terry Kennedy (Please include ``PDP-11'' in the subject line) - Paul Repacholi - Thor Lancelot Simon - John Holden - Mike Yankus - Don Stokes - David W. Peascoe - Robert Herndon - Ronald Copley - Dworkin Loki Mu:ller - Bob Kaplow, current email address unknown - Merton C. Crockett - Brian McCarthy, current email address unknown - Hans-Joachim Poehls, current email address unknown - Megan Gentry , . Web page http://world.std.com/~mbg/ - Bernd Ulmann - Roger N Wallace - Dmitry Pryanishnikov - Paul Koning - Stuart Brook - Ed Doran - Jerome Fine - Ken Kirkby - Wayne Devereux - Varga Akos Endre - Alexander Lunev - John Shelton - Robert Boers - Oleg I. KHOVAYKO - Sergey Svishchev - Alexey Chupahin - Philip Hull - Joe Smith - Eric Smith - Will Kranz ======================================================== Mark Crispin's 1986 list of PDP's With comments and spelling corrections by Charles Lasner, Bernd Ulmann, and Mike McCrohan Date: Wednesday, 20 August 1986 03:42-EDT From: Mark Crispin To: TOPS-20@SU-SCORE.ARPA, Boken@RED.RUTGERS.EDU Re: DEC's PDP's A number of people have requested my list of all the DEC PDP's, so I thought I'd bore you all with it. The PDP-1 was an 18 bit machine. It was DEC's first computer, and some of the first timesharing systems were designed for it. It's also unique in being one's complement; all later DEC computers were two's complement. Some machines, such as one of MIT's PDP-1s, were in operation until the late '70s. [Charles Lasner comments: The LINC portion of the LINC-8 and PDP-12 are one's complement!] The PDP-2 was a designation reserved for a 24 bit machine, but as far as I can tell it was never even designed and definitely none were ever built. The PDP-3 was a 36 bit machine that was designed but never built by DEC. However, Scientific Engineering Institute built one in 1960. The PDP-4 was an 18 bit machine that was intended to be a cheaper, slower alternative to the PDP-1. It was so slow that it didn't sell well, although it was interesting for its auto-incrementing memory registers. It was not program-compatible with the PDP-1, but its instruction set was the basis of DEC's future 18 bit computers. The PDP-5 was a 12 bit machine designed to be a small laboratory system. It used many of the ideas in the LINC (Laboratory Instruction Computer, designed by Lincoln Labs at MIT, some of which were built by DEC). The PDP-6 was a 36 bit machine and the first machine to implement the most wonderful computer architecture known to man. It was rather expensive and difficult to maintain, and not many were sold. As a result, DEC cancelled 36 bit computers for what was to be the first of many times. The PDP-7 was an 18 bit machine and the sucessor to the PDP-4. It was a major price/performance win over the PDP-4 and the first DEC computer to use wire-wrapping. The PDP-8 was a 12 bit machine and the sucessor to the PDP-8. [Charles Lasner comments: I assume he means -5!] It basically defined the term "minicomputer", and went through several incarnations. The original PDP-8 was followed by the extremely slow PDP-8/S (as bad as the PDP-4 was to the PDP-1, but at least the /S was program-compatible). DEC recouped with the PDP-8/I (using MSI integrated circuits) and the smaller PDP-8/L, and somewhat later came out with the "Omnibus 8" machines -- the PDP-8/E, the PDP-8/F (a half-sized version of the PDP-8/E), the PDP-8/M (an OEM version of the PDP-8/F), and the final machine, the single board PDP-8/A. The PDP-8/A still exists after a fashion as a current DEC product. The PDP-9 was an 18 bit machine and the sucessor to the PDP-7. It had a faster memory than the PDP-7 and was the first microprogrammed DEC computer. Modulo a 300 wire(!) ECO required in the first machines, the PDP-9 was a reliable machine and some are still in operation today. There was a short-lived PDP-9/L. [Comment by Bernd Ullman: As far as I know the PDP-9 had a 64 word by 36 bit read-only control-store with an access time of 212 ns (it was a transformer coupled rope memory). The first intention was to build a horizontally programmed machine but this was dropped because of the resulting word length needed for the control-words. So some (most ?) of the control signals were encoded and this led to a typical diagonally microprogrammed machine I think.] [Mike McCrohan comments: 212 ns seems fast to me for a PDP-9 in the mid 1960's when a core memory of 5 years later was cycling at 900ns, and PDP-11 instructions were at about 1 microsecond.] [Paul Koning comments: [This speed] sounds reasonable. For one thing, 800 ns was available for read-write core memory in the early 60s (CDC had it). More to the point, core ROM has very different timing. It's not exactly my field but it sounds plausible.] The PDP-10 was a 36 bit machine and the sucessor to the PDP-6. It is especially noted for its software, which represents the pinnacle of DEC software engineering and has never been equalled. The first KA10, largely installed in universities, created a whole generation of timesharing hackers. The follow-on KI10, with paging and using IC's instead of discrete components but otherwise unexciting, mostly was sold to commercial organizations. The KL10 went through several incarnations and is today the most representative of this marvelous machine. The KS10 was a small, low-speed (approximately KA10 performance) processor which was DEC's last successful implementation of this architecture. The PDP-11 was a 16-bit machine that went through more implementations and operating systems than can be counted. Presently it superceded the less powerful PDP-8 as the representative minicomputer. While the PDP-11 used octal, it was in its deep heart of hearts a hexadecimal machine, and the first indicator of the creeping IBMification of DEC that took full fruit in the VAX. [I can hear the flames now...] Rather than fight it the customers loved it; more PDP-11's have been sold than any other DEC computer (possibly more than all the others combined). The PDP-12 was a 12 bit machine and the sucessor to the PDP-8. It combined a LINC and a PDP-8 type processor in the same box and basically was a new model of the LINC-8 which was the same thing. No PDP-13 was ever designed or built. Even DEC gets superstitious. The PDP-14 was a 12 bit machine with a 1 bit register. It was used as a process control engine in applications that were felt to be too rugged for a PDP-8, and basically replaced a set of relays. Later DEC made PDP-8's suitable for this sort of thing, but it didn't stop them from the ultimate silliness of building a PDP-14 that used a PDP-8 as its console processor! [Charles Lasner comments: I remember something about a KL8-JA-oriented diagnostic that was for checking out somesuch configuration!] The PDP-15 was an 18 bit machine and the final one of this design built by DEC. More PDP-15's were built and sold than any of the others, [Charles Lasner comments: I assume he means other 18-bit DEC machines!] several incarnations including some which used a PDP-11 as a front end. Apparently the cancellation of the PDP-15 came as a great surprise to the "Tiger Team" who worked on it, although considering its general ungainliness compared to comparable pe