1080,2040,2060 ENGINEERING FUNCTIONAL SPEC - CHAP 2.8 TO: KL10 LIST, J. PARSLOW (200 FILE) TITLE: KL10 PAGING - REV 2 STATUS: FINISHED FILE: [EFS]CH2S08.SPC PDM #: 200-200-037-02 DATE: 5 DEC 75 SUPERSEDED MEMOS: KL10 PAGING PROPOSAL, D. MURPHY, 5 JUNE 73 NEW PAGING DESIGN, D. MURPHY, 31 MAY 74 SUPERSEDED SPECS: NONE ENGINEER: D. MURPHY, J. LEONARD APPROVED: EDITOR: D. MURPHY TYPIST: J. MCCARTHY REVIEWED: 6 AUG 75 DISTRIBUTED: ABSTRACT THIS CHAPTER DESCRIBES THE KL10 PAGING FACILITIES. THESE FACILITIES ARE A CONSIDERABLE ADVANCE OVER KI10 PAGING, ALTHOUGH THE KL10 ALSO PROVIDES A KI10 PAGING MODE. KL10 PAGING PROVIDES FOR EFFICIENT PROGRAM WORKING SET MANAGEMENT AND DEMAND PAGING. IT ALSO PROVIDES FOR EXTENSIVE SHARING OF DATA AND PROGRAMS ON A PAGE-BY-PAGE BASIS. REVISION HISTORY REV DESCRIPTION CHG NO ORIG DATE APPD BY DATE 1 REVIEW CHANGES 6 AUG 75 2 CLEANUP 5 DEC 75 1080,2040,2060 ENGINEERING FUNCTIONAL SPEC - CHAP 2.8 PAGE 2 COMPANY CONFIDENTIAL - KL10 PAGING - REV 2 THE KL10 PAGING FACILITIES ARE INTENDED TO SUPPORT SOPHISTICATED OPERATING SYSTEM FEATURES, INCLUDING IN PARTICULAR: 1. EFFICIENT PROGRAM WORKING SET MANAGEMENT AND DEMAND PAGING. 2. EXTENSIVE SHARING OF DATA AND PROGRAMS ON A PAGE-BY-PAGE BASIS. MUCH OF THE MECHANISM DESCRIBED HEREIN IS IMPLEMENTED BY KL10 MICROCODE RATHER THAN SPECIFIC HARDWARE. THE COMBINATION OF HARDWARE AND MICROCODE WHICH IMPLEMENTS THIS SPECIFICATION WILL BE REFERRED TO AS THE KL10 PAGER. THE KL10 ALSO SUPPORTS KI10 PAGING AS A SPECIAL MODE. KI10 PAGING IS NOT DESCRIBED IN THIS CHAPTER. THIS PAGING DESIGN ALSO SUPPORTS THE EXTENDED ADDRESSING FACILITIES OF THE KL10 PROCESSOR, AND IT IS EXTENDABLE BEYOND THE 32-SECTION IMPLEMENTATION OF THE KL10. THE PHYSICAL CORE ADDRESS FIELDS SUPPORT UP TO 27 BITS (134 MILLION WORDS) OF PHYSICAL CORE MEMORY; THE KL10 IMPLEMENTS 22 BITS (4 MILLION WORDS) OF THIS. THERE IS ALSO AN IMPLICIT LIMIT OF 2**23 (8 MILLION) PAGES PER DISK STRUCTURE (4 BILLION WORDS). N.B. "CORE" IN THIS DISCUSSION IS NOT MEANT TO SPECIFY A TECHNOLOGY, BUT A MEMORY SYSTEM WITH ACCESS TIME AND CAPACITY SIMILAR TO CORE. ADDRESS SPACES THE USER ADDRESS SPACE IS HOMOGENEOUS AND CONSISTS OF 32 EQUAL SECTIONS. SECTION 0 IS NOT TREATED IN ANY SPECIAL MANNER BY THE PAGING FACILITIES. THE SECTION TABLE FOR THE USER ADDRESS SPACE RESIDES IN THE UPT AND CONSISTS OF 32 SECTION POINTERS. THE EXEC ADDRESS SPACE ALSO CONSISTS OF 32 EQUAL SECTIONS. ITS SECTION TABLE RESIDES IN THE EPT AND CONSISTS OF 32 SECTION POINTERS. THE MONITOR SOFTWARE CAN EFFECTIVELY DIVIDE THE EXEC ADDRESS SPACE INTO PER-PROCESS AND PER-JOB AREAS THROUGH THE USE OF INDIRECT POINTERS (SEE APPENDIX), HENCE NO SUCH DIVISION NEED BE BUILT INTO THE PAGER. IN A MULTI-PROCESSING SYSTEM, EACH CPU HAS ITS OWN EPT AND HENCE ITS OWN EXEC SECTION TABLE. SECTION POINTERS A SECTION POINTER REPRESENTS AN ENTIRE SECTION, I.E., A 256K-WORD ADDRESS SPACE. IT POINTS TO A PAGE TABLE WHICH IN TURN CONTAINS POINTERS REPRESENTING EACH PAGE OF THAT SECTION. 1080,2040,2060 ENGINEERING FUNCTIONAL SPEC - CHAP 2.8 PAGE 3 COMPANY CONFIDENTIAL - KL10 PAGING - REV 2 THE SECTION POINTER MAY BE IMMEDIATE, SHARED OR INDIRECT FORMAT; IN ANY CASE, IT MUST YIELD THE PHYSICAL CORE ADDRESS OF A PAGE CONTAINING A PAGE TABLE. PAGE TABLES A PAGE TABLE IS A PAGE CONTAINING PAGE POINTERS FOR ONE SECTION. THERE ARE 512 PAGES PER SECTION AND EACH POINTER IS ONE 36-BIT WORD. HENCE A PAGE TABLE IS A FULL PAGE. STORAGE ADDRESSES (PAGE ADDRESSES) A STORAGE ADDRESS IDENTIFIES A PAGE OF PHYSICAL STORAGE IN CORE OR ON SOME OTHER MEDIUM. THE FORMAT OF THE STORAGE ADDRESS DETERMINES BOTH THE MEDIUM AND THE ADDRESS WITHIN THAT MEDIUM. STORAGE ADDRESSES ARE FOUND IN PAGE POINTERS AND IN SPT ENTRIES (BELOW), AND ARE 24-BIT QUANTITIES. 12 17 18 22 23 35 +-----------------+---------------+--------------+ ! ! ! ! +-----------------+---------------+--------------+ CORE PAGE NUMBER IF B12-17=0 IF BITS 12-17 ARE 0, THE ADDRESS REFERS TO CORE MEMORY. BITS 23-35 ARE THE PHYSICAL CORE PAGE NUMBER OF THE PAGE (B18-22 MBZ). ONLY VIRTUAL ADDRESS REFERENCES WHICH TRANSLATE TO PHYSICAL CORE ADDRESSES CAN BE COMPLETED BY THE PROCESSOR. IF BITS 12-17 ARE NOT 0, THEN THE ADDRESS IS SOMETHING OTHER THAN PHYSICAL CORE (E.G., DISK OR DRUM). A VIRTUAL ADDRESS REFERENCE WHICH TRANSLATES TO A NON-CORE ADDRESS CANNOT BE COMPLETED BY THE PROCESSOR, AND A TRAP TO THE MONITOR MUST BE INITIATED. THE FORMAT OF NON-CORE ADDRESSES IS IRRELEVANT TO THE PAGER BEYOND THE CONVENTION THAT BITS 12-17 ARE NOT 0. PAGE POINTERS THERE ARE THREE TYPES OF PAGE POINTERS, IMMEDIATE, SHARED, AND INDIRECT. THE POINTER TYPE IS ENCODED IN BITS 0-2 OF THE POINTER AS FOLLOWS: 0 NO ACCESS 1 IMMEDIATE 2 SHARED 3 INDIRECT 1080,2040,2060 ENGINEERING FUNCTIONAL SPEC - CHAP 2.8 PAGE 4 COMPANY CONFIDENTIAL - KL10 PAGING - REV 2 4-7 NOT USED, RESERVED. EACH PAGE POINTER CONTAINS ACCESS BITS WHICH DETERMINE WHAT TYPES OF REFERENCES MAY BE MADE TO THE PAGE. THE ACCESS BITS ARE HANDLED IN THE SAME WAY REGARDLESS OF WHICH OF THE THREE POINTER TYPES IS BEING INTERPRETED. P (PUBLIC,B3) IF THIS BIT IS OFF, THE PAGE MAY ONLY BE REFERENCED BY PROGRAMS RUNNING IN CONCEALED OR KERNEL MODE. SEE KI10 REFERENCE MANUAL FOR ADDITIONAL DETAILS. W (WRITE,B4) IF THIS BIT IS OFF, WRITE REFERENCES MAY NOT BE DONE TO THE PAGE. C (CACHE,B6) IF THIS BIT IS ON, DATA IN THIS PAGE MAY BE PLACED IN THE CACHE. B5,7-11 THESE BITS ARE NOT USED BY THE PAGER AND ARE RESERVED FOR FUTURE SPECIFICATION BY DEC.X IMMEDIATE POINTER AN IMMEDIATE POINTER CONTAINS THE PHYSICAL ADDRESS OF THE ASSOCIATED PAGE IN BITS 12-35. THIS POINTER TYPE IS ALSO KNOWN AS PRIVATE SINCE THE PAGE IS PRIVATE TO THE PAGE TABLE WHICH CONTAINS THE POINTER. SHARED POINTER A SHARED POINTER CONTAINS AN INDEX WHICH POINTS INTO THE SPT (SPECIAL/SHARED PAGES TABLE). THE ASSOCIATED SPT ENTRY THEN CONTAINS THE PHYSICAL ADDRESS FOR THE PAGE. THE SPT ENTRY IS FOUND AT THE PHYSICAL CORE ADDRESS GIVEN BY THE SUM OF THE SPT BASE REGISTER AND THE SPT INDEX FROM THE SHARED POINTER. THIS IS KNOWN AS A SHARED POINTER BECAUSE MANY PAGE TABLES MAY CONTAIN SHARED POINTERS TO THE SAME PHYSICAL PAGE. REGARDLESS OF THE NUMBER OF PAGE TABLES HOLDING A PARTICULAR SHARED POINTER, THE PHYSICAL ADDRESS IS RECORDED ONLY ONCE IN THE SPT, HENCE THE MONITOR MAY MOVE THE PAGE WITH ONLY ONE ADDRESS TO UPDATE. INDIRECT POINTER THE INDIRECT POINTER IDENTIFIES ANOTHER PAGE TABLE AND A POINTER WITHIN THAT PAGE TABLE. IT CAUSES THE NEW POINTER TO BE FETCHED AND INTERPRETED. HENCE, THE INDIRECT POINTER IS USED TO MAKE A PAGE OF ONE ADDRESS SPACE EXACTLY EQUIVALENT TO A PAGE OF ANOTHER ADDRESS SPACE. THE INDIRECT POINTER IDENTIFIES THE OBJECT PAGE TABLE USING AN 1080,2040,2060 ENGINEERING FUNCTIONAL SPEC - CHAP 2.8 PAGE 4 COMPANY CONFIDENTIAL - KL10 PAGING - REV 2 SPT INDEX. THE PHYSICAL ADDRESS OF THE PAGE TABLE IS FOUND IN THE ASSOCIATED SPT ENTRY JUST AS FOR A SHARED POINTER. THIS IS DONE SO THAT THE PHYSICAL ADDRESS OF A PAGE TABLE MAY BE KEPT IN ONE PLACE AND NEED NOT BE DUPLICATED IN ANY PAGE POINTERS. ONCE THE OBJECT PAGE TABLE HAS BEEN FOUND (AND DETERMINED TO BE IN CORE), THE PAGE NUMBER FIELD OF THE INDIRECT POINTER IS USED AS AN INDEX TO SELECT A NEW POINTER WORD FROM THE PAGE TABLE. THIS NEW POINTER MAY BE OF ANY OF THE THREE POINTER TYPES OR IT MAY BE NO-ACCESS. THE ACCESS BITS OF THE NEW POINTER ARE "AND"ED WITH THOSE OF THE INDIRECT POINTER. THUS ACCESS TO A PAGE IS PROHIBITED IF EITHER POINTER WOULD PROHIBIT IT. THE PAGER WILL INTERPRET INDIRECT POINTERS TO AN ARBITRARY DEPTH BUT MUST BE ABLE TO TERMINATE INDIRECT POINTER INTERPRETATION TO SERVICE A PRIORITY INTERRUPT IN THE CASE OF LONG INDIRECT CHAINS OR INDIRECT LOOPS. SPT THE SPT (SPECIAL/SHARED PAGES TABLE) HOLDS PHYSICAL ADDRESSES FOR PAGES WHICH ARE SHARED AMONG MANY PAGE TABLES (PROCESSES) OR WHICH ARE USED IN SOME SPECIAL WAY, E.G., AS PAGE TABLES. A PAGER REGISTER (AC BLOCK 6, WORD 3) HOLDS THE BASE ADDRESS OF THE SPT. THE SPT INDEX FOUND IN POINTERS IS ADDED TO THE SPT BASE ADDRESS TO FORM THE PHYSICAL CORE ADDRESS OF THE ASSOCIATED ENTRY. THE SPT ENTRY CONTAINS A PHYSICAL ADDRESS IN BITS 12-35. BITS 0-11 ARE IGNORED BY THE PAGER AND ARE USED AS A SHARE COUNT BY THE MONITOR. CORE STATUS TABLE IN ORDER TO DYNAMICALLY MANAGE CORE IN A VIRTUAL MEMORY ENVIRONMENT, IT IS EXTREMELY IMPORTANT FOR THE MONITOR TO BE ABLE TO OBTAIN INFORMATION ABOUT THE MEMORY REFERENCES GENERATED BY USER JOBS. THE CORE STATUS TABLE (CST) IS USED TO RECORD AND HOLD SUCH INFORMATION. THE BASE ADDRESS OF THE CST IS HELD IN A PAGER REGISTER (AC BLOCK 6, WORD 2). THIS IS ADDED TO THE PHYSICAL CORE PAGE NUMBER FROM A STORAGE ADDRESS TO FORM THE ADDRESS OF THE ASSOCIATED CST ENTRY. A CST ENTRY IS USED AND UPDATED IN THE FOLLOWING MANNER: 1. FETCH THE CST ENTRY. 2. IF BITS 0-5 ARE 0, THE PAGE IS INACCESSIBLE AND A TRAP TO THE MONITOR IS INITIATED. 3. THE CST ENTRY IS "AND"ED WITH A MASK BEING HELD IN A PAGER REGISTER (CSTMSK, AC BLOCK 6, WORD 0). 4. THE RESULT IS IORED WITH THE QUANTITY IN A SECOND PAGER REGISTER (CSTDATA, AC BLOCK 6, WORD 1). 1080,2040,2060 ENGINEERING FUNCTIONAL SPEC - CHAP 2.8 PAGE 6 COMPANY CONFIDENTIAL - KL10 PAGING - REV 2 5. IF THE CURRENT VIRTUAL ADDRESS REFERENCE IS A WRITE REFERENCE (AND THE ACCESS BITS PERMIT A WRITE), A 1 IS IORED INTO BIT 35. 6. THE RESULT IS STORED BACK INTO THE CST. THIS PROCEDURE ALLOWS THE MONITOR TO SET CERTAIN FIELDS AND MERGE OTHERS. TYPICALLY, ONE FIELD IS SELECTED AS AN "AGE", AND A VALUE REPRESENTING TIME IS SET INTO THIS FIELD. THUS PHYSICAL PAGES MAY BE ORDERED BY TIME OF LAST REFERENCE. ANOTHER FIELD IS TYPICALLY USED TO RECORD WHAT PROCESSES REFERENCE A PAGE. THIS IS DONE BY ASSIGNING A BIT POSITION TO EACH ACTIVE PROCESS AND PLACING A 1 IN THAT BIT POSITION IN THE PAGER DATA WORD. THUS THE CST WORD FOR A PAGE WILL HAVE ONES IN THE BIT POSITIONS OF EACH OF THE PROCESSES WHICH REFERENCED IT. ADDITIONALLY, THE MODIFIED BIT (B35) WILL BE SET IF THE PAGE HAS BEEN MODIFIED. THE MONITOR NEED NOT SWAP OUT PAGES TO WHICH ONLY READ REFERENCES HAVE BEEN DONE. POINTER INTERPRETATION FLOW THE FOLLOWING IS A DESCRIPTION OF THE POINTER INTERPRETATION ALGORITHM. IN THE FOLLOWING FLOW, THE TERM "USER" REFERS TO WHETHER AN EXEC OR USER SECTION IS BEING REFERENCED. THIS IS THE SAME AS THE PROCESS STATE BIT, EXCEPT UNDER PXCT (WHERE THE PROCESSOR CAN BE IN EXEC MODE WHILE REFERENCING A USER SECTION). THIS FLOW IS ALSO REPRESENTED BY A FLOW CHART IN THE FIGURES SECTION OF THIS DOCUMENT. 1. INITIALIZE LOCAL PAGER VARIABLES P, W, AND C TO 1. 2. FETCH SECTION POINTER. THE SECTION POINTER IS FOUND IN THE USER SECTION TABLE IN THE UPT (LOCATION USECT THROUGH USECT+37) IF THE REFERENCE IS TO A USER SECTION, AND THE EXEC SECTION TABLE IN THE EPT (LOCATION ESECT THROUGH ESECT+37) IF THE REFERENCE IS TO AN EXEC SECTION. (USECT=ESECT=440) 3. TRAP IF A NO-ACCESS SECTION POINTER. A SECTION MAY BE NON-EXISTENT FOR THE RUNNING PROCESS, IN WHICH CASE THE SECTION POINTER WILL BE 0. BITS 0-2 OF THE SECTION POINTER ARE USED AS A CODE FIELD JUST AS WITH PAGE POINTERS. CODE 0 IS NO-ACCESS, CODE 1 IS IMMEDIATE, CODE 2 (SHARE) IS NORMAL SECTION POINTER, CODE 3 (INDIRECT) MAY ALSO BE USED, OTHER CODES ARE NOT DEFINED. 4. UPDATE ACCESS BITS. AND P, W, C (LOCAL PAGER VARIABLES) WITH SECTION POINTER BITS 3, 4, 6 RESPECTIVELY. 5. IF THE CODE IN BITS 0-2 IS 1, BITS 23-35 CONTAIN THE PAGE TABLE ADDRESS. OTHERWISE, FETCH THE PAGE TABLE 1080,2040,2060 ENGINEERING FUNCTIONAL SPEC - CHAP 2.8 PAGE 7 COMPANY CONFIDENTIAL - KL10 PAGING - REV 2 PHYSICAL ADDRESS. FETCH FROM THE PHYSICAL CORE ADDRESS GIVEN BY THE SUM OF THE SPT BASE ADDRESS AND THE SPT INDEX. THE SPT INDEX IS BITS 18-35 OF THE LAST POINTER FETCHED (A SECTION POINTER OR AN INDIRECT POINTER). 6. TRAP IF THE PAGE TABLE IS NOT IN CORE. IF THE PHYSICAL ADDRESS OBTAINED IN STEP 5 DOES NOT CONTAIN 0 IN BITS 12-17, THEN THE PHYSICAL ADDRESS IS NOT A CORE ADDRESS AND A TRAP IS INITIATED. IF THE SECTION POINTER WAS INDIRECT, FETCH A NEW SECTION POINTER FROM THIS PAGE TABLE, THE ENTRY GIVEN BY BITS 9-17 OF THE INDIRECT POINTER, AND GO TO 3. 7. CHECK AND UPDATE THE CST FOR THE PAGE TABLE. FETCH FROM THE PHYSICAL CORE ADDRESS GIVEN BY THE SUM OF THE CST BASE ADDRESS AND THE PHYSICAL CORE PAGE NUMBER. TRAP IF BITS 0-5 OF THE CST ENTRY ARE 0. OTHERWISE, AND CSTMSK, IOR CSTDATA, AND STORE THE RESULT BACK INTO CORE. THE MODIFIED BIT SHOULD NOT BE CHANGED HERE. 8. FETCH THE PAGE POINTER. THE PAGE POINTER IS FETCHED FROM THE PHYSICAL CORE ADDRESS CONSISTING OF THE CORE PAGE NUMBER OF THE PAGE TABLE IN BITS 14-26, AND THE CURRENT VIRTUAL PAGE NUMBER IN BITS 27-35. THE CURRENT PAGE NUMBER CAME FROM VMA BITS 18-26 OR FROM BITS 9-17 OF THE LAST INDIRECT POINTER. 9. UPDATE ACCESS BITS. THE P, W, AND C BITS ARE ANDED WITH THE RESPECTIVE PAGER VARIABLES. 10. DISPATCH ON POINTER TYPE. IF A NO-ACCESS POINTER (CODE 0), INITIATE A TRAP. IF AN INDIRECT POINTER, (CODE 3) TAKE BITS 9-17 AS THE NEW CURRENT PAGE NUMBER, AND TAKE BITS 18-35 AS AN SPT INDEX IDENTIFYING A NEW PAGE TABLE. LOOP BACK TO STEP 5. IF A SHARE POINTER, FETCH THE SPT ENTRY GIVEN BY THE SUM OF THE SPT BASE REGISTER AND BITS 18-35 OF THE SHARE POINTER. IF AN IMMEDIATE POINTER, CONTINUE TO STEP 11. 11. TRAP IF PAGE NOT IN CORE. IF BITS 12-17 OF THE PHYSICAL ADDRESS ARE NOT 0, THE ASSOCIATED PAGE IS NOT IN CORE AND A TRAP TO THE MONITOR IS INITIATED. 12. CHECK AND UPDATE THE CST FOR THE PAGE. FETCH FROM THE PHYSICAL CORE ADDRESS GIVEN BY THE SUM OF THE CST BASE ADDRESS AND THE PHYSICAL CORE PAGE NUMBER. TRAP IF BITS 0-5 OF THE CST ENTRY ARE 0. OTHERWISE, AND CSTMSK, IOR CSTDATA, AND IOR B35 IF A WRITE REFERENCE 1080,2040,2060 ENGINEERING FUNCTIONAL SPEC - CHAP 2.8 PAGE 8 COMPANY CONFIDENTIAL - KL10 PAGING - REV 2 AND W=1. STORE THE RESULT BACK INTO CORE. 13. COMPLETE THE VIRTUAL ADDRESS REFERENCE AND/OR LOAD PAGING MEMORY. INITIATE ILLEGAL WRITE TRAP IF WRITE AND NOT-W. THE PHYSICAL ADDRESS FOR THE REFERENCE CONSISTS OF THE PHYSICAL CORE PAGE NUMBER IN BITS 14-26, AND VMA BITS 27-35 IN BITS 27-35. INSTRUCTIONS RELEVANT TO PAGING SEE CHAP 2.6 OF KL10 FUNCTIONAL SPECS, KL10 INTERNAL IO INSTRUCTIONS, FOR ADITIONAL INFORMATION. 1. LOAD UBR (DATAO PAG,) LOAD EBR (CONO PAG,). 2. CLEAR PAGING MEMORY (DATAO PAG, CONO PAG,). 3. CLEAR PAGING MEMORY ENTRY FOR MONITOR VIRTUAL ADDRESS E (CLRPT E). 4. PAGING ON/OFF (CONO PAG,). 5. DECLARE SPT BASE ADDRESS; CST BASE ADDRESS; CSTMSK; CSTDATA. (DONE AS DEPOSITS INTO RESERVED AC BLOCK.) PAGE FAIL DATA THE FOLLOWING DATA IS STORED WHEN A PAGE FAIL TRAP IS INITIATED: 1. VIRTUAL ADDRESS OF REFERENCE 2. USER BIT, PUBLIC BIT, WRITE REFERENCE BIT 3. PAGE FAIL CODE SPECIFIC PAGE FAIL CODES ARE GENERATED AND STORED IN THE PAGE FAIL WORD FOR THE FOLLOWING CONDITIONS: 1. PROPRIETARY VIOLATION 2. REFILL ERROR 3. ADDRESS COMPARE 4. PAGE TABLE PARITY ERROR 5. MEMORY DATA PARITY ERROR 1080,2040,2060 ENGINEERING FUNCTIONAL SPEC - CHAP 2.8 PAGE 9 COMPANY CONFIDENTIAL - KL10 PAGING - REV 2 ALL OTHER PAGE FAIL CONDITIONS STORE ONLY THE DATA DESCRIBING THE REFERENCE (ADDRESS, USER, PUBLIC, WRITE) AND THE SOFTWARE WILL DETERMINE THE CAUSE OF THE PAGE FAIL AND THE PROPER ACTION. 1080,2040,2060 ENGINEERING FUNCTIONAL SPEC - CHAP 2.8 PAGE 10 COMPANY CONFIDENTIAL - KL10 PAGING - REV 2 KL10 PAGING - WORD FORMATS SECTION POINTER THE SECTION POINTER IS FOUND IN THE USER OR EXEC SECTION TABLE. (PART OF UPT OR EPT.) SECTION POINTER PROVIDES (VIA THE SPT) THE PHYSICAL ADDRESS OF THE PAGE TABLE FOR THE GIVEN SECTION. CODE: 0 NO-ACCESS (TRAP) 1 IMMEDIATE 2 SHARE 3 INDIRECT 4-7 UNUSED, RESERVED 0 1 2 3 4 5 6 18 35 +----+-+-+-+-+---------+-------------------------+ !CODE!P!W! !C!/////////! PAGE TABLE IDENTIFIER ! !010 ! ! ! ! !/////////! (SPT INDEX) ! +----+-+-+-+-+---------+-------------------------+ NORMAL SECTION POINTER (CODE = 2) 0 2 3 4 5 6 9 18 35 +----+-+-+-+-+---+-----------+------------------------+ !CODE!P!W! !C!///!SECTION !SECTION TABLE IDENTIFIER! !011 ! ! ! ! !///!TABLE INDEX! (SPT INDEX) ! +----+-+-+-+-+---+-----------+------------------------+ INDIRECT SECTION POINTER (CODE = 3) 1080,2040,2060 ENGINEERING FUNCTIONAL SPEC - CHAP 2.8 PAGE 11 COMPANY CONFIDENTIAL - KL10 PAGING - REV 2 PAGE POINTERS FOUND IN PAGE TABLES 0 1 2 3 4 5 6 12 35 +----+-+-+-+-+----+------------------------------+ !CODE!P!W! !C!////! PHYSICAL ADDRESS OF PAGE ! !001 ! ! ! ! !////! ! +----+-+-+-+-+----+------------------------------+ IMMEDIATE POINTER (CODE FIELD = 1) B12-35 GIVE PHYSICAL ADDRESS OF PAGE IF B12-17 >< 0, PAGE NOT IN CORE-TRAP IF B12-17 = 0, B23-35 GIVE CORE PAGE NUMBER OF PAGE, B18-22 MBZ 0 2 3 6 18 35 +-----+-------+---------+------------------------+ !CODE !SAME AS!/////////! SPT INDEX ! !010 ! IMMED.!/////////! ! +-----+-------+---------+------------------------+ SHARED POINTER (CODE FIELD = 2) B18-35 GIVE SPT INDEX (SPTX). SPTX + SPT BASE ADDRESS = PHYSICAL CORE ADDRESS OF WORD HOLDING PHYSICAL ADDRESS OF PAGE. 1080,2040,2060 ENGINEERING FUNCTIONAL SPEC - CHAP 2.8 PAGE 12 COMPANY CONFIDENTIAL - KL10 PAGING - REV 2 0 1 2 3 6 9 17 18 35 +----+--------+---+-------+----------------------+ !CODE!SAME AS !///! PAGE ! PAGE TABLE IDENTIFIER! !011 ! IMMED. !///!NUMBER ! (SPT INDEX) ! +----+--------+---+-------+----------------------+ INDIRECT POINTER (CODE FIELD = 3) THIS POINTER TYPE CAUSES ANOTHER POINTER TO BE FETCHED AND INTERPRETED. THE NEW POINTER IS FOUND IN WORD N (B9-17) OF THE PAGE ADDRESSED BY C(SPT + SPTX). SPT ENTRY FOUND IN THE SPT, I.E., WHEN FETCHING C(SPT +SPTX) 12 35 +--------------------+---------------------------+ !////////////////////! PHYSICAL ADDRESS OF PAGE ! !////////////////////! OR PAGE TABLE ! +--------------------+---------------------------+ B12-35 GIVE PHYSICAL ADDRESS OF PAGE. THE BASE ADDRESS (PHYSICAL CORE ADDRESS) OF THE SPT RESIDES IN ONE AC OF THE RESERVED AC BLOCK. 1080,2040,2060 ENGINEERING FUNCTIONAL SPEC - CHAP 2.8 PAGE 13 COMPANY CONFIDENTIAL - KL10 PAGING - REV 2 PHYSICAL STORAGE ADDRESS FOUND IN B12-35 OF IMMEDIATE POINTERS AND SPT ENTRIES. 12 17 18 23 35 +---------+----+-----------------+ ! !MBZ ! CORE PAGE NUMBER! ! ! ! IF B12-17 = 0 ! +---------+----+-----------------+ IF B12-17 = 0, THEN B23-35 ARE CORE PAGE NUMBER (I.E., B14-26 OF PHYSICAL CORE ADDRESS) OF PAGE AND B18-22 MBZ. IF B12-17 >< 0, THEN ADDRESS IS NOT CORE AND PAGER TRAPS. CORE STATUS TABLE ENTRY FOUND WHEN FETCHING C(CBR + CORE PAGENO) 0 5 32 34 35 +-------+-------------------------------+------+-+ ! CODE ! ! !M! +-------+-------------------------------+------+-+ B0-5 ARE CODE FIELD: 0 - UNAVAILABLE, TRAP 1-77 - AVAILABLE B32-34 RESERVED FOR FUTURE HARDWARE SPECIFICATION. B35 IS "MODIFIED" BIT, SET ON ANY WRITE REF TO PAGE. WHENEVER A CORE PAGE NUMBER (PHYS. ADR WITH B12-17=0) IS FOUND DURING POINTER INTERPRETATION, THE CST WORD AT CBR + CORE PAGENO IS UPDATED AS FOLLOWS: 1. FETCH C(CBR+CORE PAGENO) 2. TRAP IF B0-5 =0 3. AND WITH MASK FROM RESERVED AC BLOCK 4. IOR WITH DATA FROM RESERVED AC BLOCK 5. IOR B35 IF WRITE REFERENCED 1080,2040,2060 ENGINEERING FUNCTIONAL SPEC - CHAP 2.8 PAGE 14 COMPANY CONFIDENTIAL - KL10 PAGING - REV 2 QUANTITIES IN HARDWARE REGISTERS (RESERVED AC BLOCK) SPT SPT BASE REGISTER 14 35 +--------------------------------+ ! PHYSICAL CORE WORD ADDRESS ! +--------------------------------+ CBR CST BASE REGISTER 14 35 +--------------------------------+ ! PHYSICAL CORE WORD ADDRESS ! +--------------------------------+ CSTMSK CST UPDATE MASK 0 32 35 +------------------------------------------+---+-+ ! MASK !111!1! +------------------------------------------+---+-+ ANDED WITH CST WORD DURING UPDATE (B23-35 MUST BE ALL 1'S TO PRESERVE EXISTING CST INFORMATION) ALL UNSPECIFIED BITS AND FIELDS ARE RESERVED FOR FUTURE SPECIFICATION BY DEC. 1080,2040,2060 ENGINEERING FUNCTIONAL SPEC - CHAP 2.8 PAGE 15 COMPANY CONFIDENTIAL - KL10 PAGING - REV 2 HERE WHEN PAGING CACHE REQUIRES TRANSLATION INFORMATION ! +----------------------+ SYMBOL MEANING ! VMA<13-17>->SECT NO; ! -> "GOES TO" ! VMA<18-26>->PAGE NO; ! ^ "ANDED WITH" !1 -> P; 1 -> W; 1 -> C! V "ORED WITH" +----------------------+ ' "CONCATENATED WITH" ! + "ADDED TO" V C( ) THE WORD WHOSE PHYSICAL / \ ADDRESS IS GIVEN BY THE YES / USER \ NO EXPRESSION IN PARENTHESIS +-----/ ADDRESS \-----+ !USER \ ? / EXEC! ! \ / ! ! \ / ! +---------------+ ! V ! ! ! +--------------+ +--------------+ +----------------------+ ! ! C(UBF'USECT+ ! ! C(EBR'ESECT+ ! ! C(AR<23-35>'SECTNO) ! ! !SECT NO) -> AR! !SECT NO) -> AR! ! -> AR ! ! +--------------+ +--------------+ +----------------------+ ! ! ! ! ! +---------------+--------------------+ ! ! ! V ! +------------------+ ! ! AR<0-2> -> TYPE; ! P ENABLES ACCESS BY PUBLIC ! ! P ^ AR<3> -> P; ! W ENABLES WRITE ACCESS ! ! W ^ AR<4> -> W; ! C ENABLES DATA INTO CACHE ! ! C ^ AR<6> -> C; ! ! ! TEST TYPE ! ! +------------------+ ! ! ! V ! +-----------------------------------------------+ ! !TYPE=4-7 !TYPE=0 !TYPE=1 !TYPE=2 !TYPE=3 ! V ! !IMMEDIATE !SHARED !INDIRECT ! UNDEFINED ! ! ---------- ! +-------------------+ ! V ! / INDIRECT \! !AR<9-17> ->SECT NO;! ! TRAP ! \ PAGE /! ! C(SBR+AR<18-35>) ! ! ! ---------- ! ! -> AR ! ! ! ! ! +-------------------+ ! ! +---->! ! ! ! ! / \ ! ! +--------------------+ / \ ! ! ! C(SBR+AR<18-35>) ! NO / \ YES! ! ! -> AR ! +--/AR<12-17>\---! ! +--------------------+ ! \ = 0 ? / !<------------! ! \ / ! TRAP \ / V V 1080,2040,2060 ENGINEERING FUNCTIONAL SPEC - CHAP 2.8 PAGE 16 COMPANY CONFIDENTIAL - KL10 PAGING - REV 2 ! ! / \ / \ NO / \ +------/AR<12-17>\ ! \ = 0 ? / TRAP \ / \ / V ! YES +-------------------+ !AR<23-35>->PT PAGE;! ! C(CBR + PT PAGE) ! ! -> AR ! +-------------------+ ! / \ / \ YES / \ +------/ AR<0-5> \ ! \ = 0 ? / TRAP \ / \ / V ! NO V +--------------------------+ !(AR ^ CST MASK)V CST DATA ! THIS CST UPDATE IS FOR THE ! -> AR; ! PAGE CONTAINING THE PAGE ! STORE; ! TABLE. SINCE NEITHER THE ! C (PT PAGE'PAGE NO) ! PAGER NOR THE CURRENT ! ->AR; ! REFERENCE IS MODIFYING THE ! P ^ AR<3> -> P ! PAGE TABLE PAGE, WE DO ! W ^ AR<4> -> W ! NOT SET BIT 35 OF THE CST ! C ^ AR<6> -> C ! ENTRY, EVEN ON A WRITE ! AR<0-2> -> TYPE ! REFERENCE. ! TEST TYPE ! +--------------------------+ ! V +--------+-------+---------+---------------------+ !TYPE=4-7!TYPE=0 !TYPE=1 !TYPE=2 !TYPE=3 V ! !IMMEDIATE!SHARE !INDIRECT UNDEFINED! ! ! ! V ! +---------------+ +----------------------+ TRAP ! !C(SBR+AR<18-35>! ! AR<9-17> -> PAGE NO ! ! ! -> AR ! +----------------------+ ! +---------------+ ! !<--------! -------- ! (INDIRECT) (wrong!!! - JW) V -------- 1080,2040,2060 ENGINEERING FUNCTIONAL SPEC - CHAP 2.8 PAGE 17 COMPANY CONFIDENTIAL - KL10 PAGING - REV 2 ! V / \ NO / \ +------/AR<12-17> \ ! \ = 0 ? / TRAP \ / \ / ! =YES V +------------------------+ ! AR<23-35> -> PAGE NO; ! ! C(CBR + PAGE NO) -> AR ! +------------------------+ ! V / \ YES / \ +------/ AR<0-5> \ ! \ = 0 ? / TRAP \ / \ / ! NO V +---------------------+ "S" IS USED BY SOFTWARE TO TELL ! AR ^ CSTMASK -> AR; ! WHETHER THE PAGE IS LOGICALLY ! W -> S ! WRITABLE. "W" IS USED BY HARD- +---------------------+ WARE TO TELL WHETHER SPECIAL ! ACTION IS NEEDED ON A WRITE. V / \ / \ = 1 (WRITABLE) / W = 1 \------------------+ \ ? / ! \ / V \ / / \ ! NOT / \ YES V WRITABLE / WRITE \------+ / \ \ REF / ! YES / \ \ ? / ! +------/ WRITE \ \ / ! ! \ REF ? / ! NO ! TRAP \ / V ! \ / / \ ! ! NO / \ YES ! ! NO +-----/ AR<35> \----->! ! ! \ = 1 ? /WRITTEN! ! +---------+ \ / +--------------+ ! ! 0 -> W ! \ / ! 1 -> AR<35> ! ! +---------+ +--------------+ ! ! ! +----------->!<-----------------------+ ! ! 1080,2040,2060 ENGINEERING FUNCTIONAL SPEC - CHAP 2.8 PAGE 18 COMPANY CONFIDENTIAL - KL10 PAGING - REV 2 ! V +---------------------+ ! AR V CST DATA -> AR;! ! STORE ! +---------------------+ ! +-----------------------+ ! P'W'S'C'PAGE NO ! ! -> PAGING CACHE ! +-----------------------+ ! +-------------+ ! RESTART ! ! FAULTED ! ! REFERENCE ! +-------------+ 1080,2040,2060 ENGINEERING FUNCTIONAL SPEC - CHAP 2.8 PAGE 19 COMPANY CONFIDENTIAL - KL10 PAGING - REV 2 APPENDIX I - EPT/UPT SYMBOLS USED ESECT = 440 SECTION TABLE FOR EXEC SECTIONS 0--37 USECT = 440 SECTION TABLE FOR USER SECTIONS 0-37 APPENDIX II THE FOLLOWING DISCUSSES SOME OF THE DESIGN AND IMPLEMENTATION ISSUES OF THE PAGER. CACHED PAGING DATA THE KL10 HAS A "PAGING MEMORY" WHICH HOLDS VIRTUAL-TO-PHYSICAL MAPPING INFORMATION. THIS IS EFFECTIVELY A CACHE OF PAGING DATA WHICH HAS BEEN FETCHED FROM MEMORY AND/OR DETERMINED BY POINTER INTERPRETATION. NOTE, HOWEVER, THAT IT IS TOTALLY DISTINCT FROM THE MEMORY CACHE, USUALLY REFERRED TO AS SIMPLY "THE CACHE". WHEN A VIRTUAL ADDRESS REFERENCE IS REQUESTED, THE PAGING MEMORY IS FIRST CHECKED TO SEE IF THE CORRESPONDING PHYSICAL ADDRESS IS PRESENT. IF IT IS, THE REFERENCE CAN PROCEED WITH NO DELAY. IF IT IS NOT, THE DATA MUST BE OBTAINED FROM CORE. THE KL10 PAGING MEMORY IS IMPLEMENTED AS A TABLE WITH ONE ENTRY FOR EACH OF THE 512 PAGES OF THE VIRTUAL ADDRESS SPACE. (THE KI10 IMPLEMENTED THE EQUIVALENT FUNCTION WITH ASSOCIATIVE MEMORY.) THE USER AND EXEC ADDRESS SPACES USE THE SAME 512 ENTRIES, BUT THE INDEX IS OFFSET DIFFERENTLY SO AS TO REDUCE CONFLICTS. AT ANY TIME THEN, THE PAGING MEMORY WILL BE HOLDING MAPPING INFORMATION FOR MOST OF THE PAGES ACTIVELY BEING USED BY THE RUNNING PROGRAM. WHEN THE MONITOR TAKES ANY ACTION WHICH WOULD INVALIDATE SOME EXISTING VIRTUAL-TO-PHYSICAL ADDRESS ASSOCIATIONS, THE PAGING MEMORY MUST BE PARTIALLY OR COMPLETELY CLEARED. SUCH CASES INCLUDE: 1. CHANGE OF USER PROCESS - THE ENTIRE USER ADDRESS SPACE CHANGES, SO THE ENTIRE PAGING MEMORY MUST BE CLEARED. 2. REMOVAL OF ONE PAGE FROM CORE OR REMOVAL OF A POINTER FROM THE USER PROCESS PAGE TABLE - THE ENTIRE PAGING MEMORY MUST BE CLEARED SINCE SHARED AND INDIRECT POINTERS MAY HAVE CAUSED THE ONE PHYSICAL PAGE TO APPEAR IN SEVERAL VIRTUAL PAGES. 3. IN SOME CASES, THE MONITOR WILL MAP A PAGE INTO THE EXEC MAP FOR LOCAL USE. WHEN THIS PAGE IS UNMAPPED, ONLY THAT ONE ASSOCIATION NEED BE CLEARED FROM THE PAGING MEMORY. THE PAGER PROVIDES A FUNCTION TO CLEAR THE ASSOCIATION FOR A PARTICULAR VIRTUAL ADDRESS. THIS MAY BE USED IN THIS CASE TO REDUCE SUBSEQUENT RELOAD 1080,2040,2060 ENGINEERING FUNCTIONAL SPEC - CHAP 2.8 PAGE 20 COMPANY CONFIDENTIAL - KL10 PAGING - REV 2 OVERHEAD. IN KL10 PAGING MODE, WHEN THE PAGING MEMORY FAILS TO CONTAIN THE DATA FOR THE REQUESTED VIRTUAL ADDRESS, A SPECIAL TRAP IN THE MICROCODE OCCURS. AFTER SAVING VULNERABLE ACTIVE EBOX DATA, THE MICROCODE INVOKES THE POINTER TRACING AND INTERPRETATION ALGORITHM DESCRIBED ABOVE. IF THE POINTER INTERPRETATION YIELDS A VALID CORE ADDRESS, IT AND THE ACCESS INFORMATION ARE LOADED INTO THE PAGING MEMORY. THEN THE EBOX ACTIVE REGISTERS ARE RESTORED AND THE ORIGINAL MEMORY REFERENCE IS REQUESTED AGAIN. THE PAGER IS REQUIRED TO MAINTAIN THE MODIFIED BIT IN THE CORE STATUS TABLE. THIS MEANS THAT THE FIRST WRITE REFERENCE TO A PAGE MUST BE DETECTED EVEN IF PREVIOUS READ REFERENCES HAVE BEEN MADE. THE MICROCODE IMPLEMENTS THIS AS FOLLOWS: ON A PAGING MEMORY RELOAD, THE WRITE ACCESS (W) BIT IS SET IN THE PAGING MEMORY ONLY IF THE CURRENT MEMORY REFERENCE IS A WRITE (AND WRITE IS LEGAL FOR THE PAGE). THUS IS THE FIRST REFERENCE TO A PAGE IS READ, THE W BIT IN THE CORRESPONDING PAGING MEMORY ENTRY WILL BE SET TO 0, AND A SUBSEQUENT WRITE REFERENCE WILL CAUSE ANOTHER TRAP TO THE MICROCODE. ON THIS SECOND TRAP, THE POINTER INTERPRETATION WILL BE REPEATED AND THE PGING MEMORY RELOADED, THIS TIME WITH THE W BIT SET. IT HAS BEEN SUGGESTED THAT THE MICROCODE COULD USE THE UNUSED BIT (FORMERLY THE S BIT) IN THE PAGING MEMORY TO RECORD WHETHER OR NOT THE PAGE IS WRITABLE AND THEREBY AVOID THE SECOND POINTER TRACE IN THE WRITE-AFTER-READ CASE. THE PERFORMANCE IMPROVEMENT APPEARS TO BE VERY SMALL HOWEVER AND AT PRESENT DOES NOT SEEM WORTH THE ADDITIONAL MICROCODE WHICH WOULD BE REQUIRED. CACHE CONSIDERATIONS IN A ONE-CPU CONFIGURATION, IT DOES NOT MATTER LOGICALLY WHETHER MICROCODE PAGING REFERENCES ARE CACHED. SINCE THE PAGING MEMORY IS AVAILABLE TO HOLD PAGING DATA, IT WOULD SEEM REDUNDANT TO ALSO HOLD PAGE POINTERS IN THE CACHE. ALSO, IT APPEARS UNLIKELY THAT REFERENCES ARE MADE TO PAGE POINTERS VERY OFTEN. ON THE OTHER HAND, THE SECTION 0 SECTION POINTERS (EXEC AND USER) AND THE ASSOCIATED SPT WORDS ARE REFERENCED ON EVERY PAGE MEMORY RELOAD. HENCE, IT IS UNCLEAR WHETHER A PERFORMANCE ADVANTAGE IS OBTAINED BY CACHING OR NOT CACHING PAGE REFILL REFERENCES. MULTI-CPU CONSIDERATIONS IN A MULTI-CPU CONFIGURATION USING KL10S, EACH PROCESSOR WOULD HAVE ITS OWN PAGING MEMORY, AND IN GENERAL, ALL OF THEM MUST BE 1080,2040,2060 ENGINEERING FUNCTIONAL SPEC - CHAP 2.8 PAGE 21 COMPANY CONFIDENTIAL - KL10 PAGING - REV 2 CLEARED ON ANY EVENT WHICH REQUIRES CLEARING ONE. THEREFORE THE MONITOR MUST HAVE A SIGNAL MECHANISM TO QUICKLY REQUEST THE OTHER PROCESSORS TO EXECUTE THE APPROPRIATE PAGER INSTRUCTIONS. THE CODE FIELD OF THE CORE STATUS TABLE MAY BE USED TO PREVENT ACCESS TO CERTAIN PAGES BY OTHER PROCESSORS WHEN ONE PROCESSOR BEGINS SOME HOUSEKEEPING FUNCTION ON THOSE PAGES (E.G., SWAPPING OUT TO DISK). IT DOES NOT, HOWEVER, PROVIDE ANY MECHANISM TO LIMIT ACCESS TO EXACTLY ONE PROCESSOR. IN A MULTI-CPU CONFIGURATION, THE SEVERAL PROCESSORS WILL BE UPDATING THE CORE STATUS TABLE SIMULTANEOUSLY, AND SOME MECHANISM (E.G., READ-PAUSE-WRITE) MUST BE USED TO ENSURE THAT DATA IS NOT LOST BECAUSE OF TWO PROCESSORS SIMULTANEOUSLY UPDATING THE SAME ENTRY. OBVIOUSLY, MICROCODE CST REFERENCES CANNOT BE CACHED, AND THE MONITOR MUST ENSURE THAT PROGRAM REFERENCES TO THE CST ARE ALSO NOT CACHED. IT IS DESIRABLE THAT ALL MICROCODE PAGING REFERENCES BE UNCACHED IN A MULTI-CPU CONFIGURATION, OTHERWISE THE SOFTWARE MUST DO A CACHE CLEAR ALSO EVERY TIME IT DOES A PAGING MEMORY CLEAR OF ANOTHER PROCESSOR. DIVISION OF EXEC ADDRESS SPACE TYPICALLY THE MONITOR USES AREAS OF THE EXEC ADDRESS SPACE IN DISTINCT WAYS: 1. SYSTEM-WIDE CODE AND DATA. E.G., THE MONITOR CODE, SCHEDULER AND SWAPPER DATA BASES, ETC. 2. PER-JOB DATA. E.G., OPEN FILE DATA, FORK STRUCTURE DATA, ETC. 3. PER-PROCESS DATA. E.G., LOCAL STACK, LOCAL VARIABLES, ETC. IN ADDITION TO PERMANENT CONTENTS, EACH OF THESE AREAS WILL ALSO HAVE FILE OR PROCESS PAGES DYNAMICALLY MAPPED IN AS NEEDED. THE INDIRECT POINTER MECHANISM MAY BE USED TO CONFIGURE THE EXEC ADDRESS SPACE IN THIS MANNER, AND IT DOES NOT REQUIRE THAT ANY BOUNDARIES BE WIRED INTO HARDWARE (AS ON THE KI10, EXEC PAGES 340-377). TO IMPLEMENT THE DIVISION ABOVE, THE MONITOR WOULD HAVE THREE PARTIAL PAGE TABLES: 1. THE SYSTEM MONITOR MAP RESIDING IN RESIDENT STORAGE; 2. THE JOB MAP RESIDING IN A PAGE SWAPPED WITH THE JOB; 3. THE PROCESS MAP RESIDING IN A PAGE SWAPPED WITH THE PROCESS. 1080,2040,2060 ENGINEERING FUNCTIONAL SPEC - CHAP 2.8 PAGE 22 COMPANY CONFIDENTIAL - KL10 PAGING - REV 2 THE THREE MAPS WOULD COVER MUTUALLY EXCLUSIVE AREAS OF THE MONITOR ADDRESS SPACE. EACH WOULD HAVE AN SPT SLOT ASSIGNED TO HOLD ITS PHYSICAL CORE ADDRESS. ALL POINTER TRACES WOULD FIRST REFERENCE THE SYSTEM MONITOR MAP AFTER HAVING INTERPRETED THE EXEC SECTION 0 POINTER. FOR SYSTEM-WIDE PAGES, THE MAP WOULD CONTAIN A NORMAL PAGE POINTER TO THE APPROPRIATE PAGE. FOR PER-JOB PAGES, THE MAP WOULD CONTAIN AN INDIRECT POINTER TO THE JOB MAP, AND FOR PER-PROCESS PAGES, THE MAP WOULD CONTAIN AN INDIRECT POINTER TO THE PROCESS MAP. IN ORDER TO AVOID CHANGING ALL OF THE PER-JOB AND PER-PROCESS POINTERS ON A CONTEXT SWITCH, TWO SPT ENTRIES WOULD BE RESERVED FOR THE "CURRENT" JOB MAP AND PROCESS MAP ADDRESSES, AND THE JOB AND PROCESS POINTERS WOULD ALWAYS USE THESE RESERVED ENTRIES. THAT IS, WHEN ANY PROCESS IS STARTED, ITS JOB MAP CORE ADDRESS IS COPIED INTO THE RESERVED JOB SPT ENTRY, AND ITS PROCESS MAP CORE ADDRESS IS COPIED INTO THE RESERVED PROCESS SPT ENTRY. THESE SPT ENTRIES BECOME IN EFFECT TWO BASE REGISTERS FOR THE TWO MAPS, AND THE MONITOR MUST SET THEM JUST AS THOUGH THEY WERE IMPLEMENTED IN HARDWARE. [END OF KLPAG.SPC]